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521d6a1785
Previously, instructions which could be expressed as VOP3 in addition to another encoding had a _e64 suffix on the tablegen record name, while those only available as VOP3 did not. With this patch, all VOP3s will have the _e64 suffix. The assembly does not change, only the mir. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D94341 Change-Id: Ia8ec8890d47f8f94bbbdac43745b4e9dd2b03423
37 lines
1.2 KiB
YAML
37 lines
1.2 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=livevars,phi-node-elimination,twoaddressinstruction -verify-machineinstrs -o - %s | FileCheck %s
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# This used to fail under ASAN enabled build because we didn't update LiveVariables in SIInstrInfo::convertToThreeAddress()
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# CHECK: _amdgpu_ps_main
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---
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name: _amdgpu_ps_main
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alignment: 1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr2, $vgpr2, $vgpr3
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%0:vgpr_32 = COPY $vgpr3
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%1:vgpr_32 = COPY $vgpr2
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S_BRANCH %bb.3
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bb.1:
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%2:vgpr_32 = V_MAC_F32_e32 0, %0, %1, implicit $mode, implicit $exec
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%3:vgpr_32 = V_MED3_F32_e64 0, %1, 0, %2, 0, %2, 0, 0, implicit $mode, implicit $exec
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bb.2:
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%4:vgpr_32 = PHI %5, %bb.3, %3, %bb.1
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SI_END_CF %6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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EXP_DONE 0, %4, %4, %4, %4, -1, 0, 15, implicit $exec
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S_ENDPGM 0
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bb.3:
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successors: %bb.1, %bb.2
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%5:vgpr_32 = V_MAC_F32_e32 0, %1, %0, implicit $mode, implicit $exec
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%7:vgpr_32 = V_CVT_I32_F32_e32 %5, implicit $mode, implicit $exec
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%8:sreg_64 = V_CMP_NE_U32_e64 1, %7, implicit $exec
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%6:sreg_64 = SI_IF %8, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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S_BRANCH %bb.1
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...
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