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f58aee7cea
Summary: Also explicitly port over some tests in llvm.amdgcn.image.* that were missing. Some tests are removed because they no longer apply (i.e. explicitly testing building an address vector via insertelement). This is in preparation for the eventual removal of the old-style intrinsics. Some additional notes: - constant-address-space-32bit.ll: change some GCN-NEXT to GCN because the instruction schedule was subtly altered - insert_vector_elt.ll: the old test didn't actually test anything, because %tmp1 was not used; remove the load, because it doesn't work (Because of the amdgpu_ps calling convention? In any case, it's orthogonal to what the test claims to be testing.) Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf Reviewers: arsenm, rampitec Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D48018 llvm-svn: 335229
104 lines
4.3 KiB
LLVM
104 lines
4.3 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL:{{^}}row_filter_C1_D0:
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define amdgpu_kernel void @row_filter_C1_D0() #0 {
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entry:
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br i1 undef, label %for.inc.1, label %do.body.preheader
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do.body.preheader: ; preds = %entry
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%tmp = insertelement <4 x i32> zeroinitializer, i32 undef, i32 1
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br i1 undef, label %do.body56.1, label %do.body90
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do.body90: ; preds = %do.body56.2, %do.body56.1, %do.body.preheader
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%tmp1 = phi <4 x i32> [ %tmp6, %do.body56.2 ], [ %tmp5, %do.body56.1 ], [ %tmp, %do.body.preheader ]
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%tmp2 = insertelement <4 x i32> %tmp1, i32 undef, i32 2
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%tmp3 = insertelement <4 x i32> %tmp2, i32 undef, i32 3
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br i1 undef, label %do.body124.1, label %do.body.1562.preheader
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do.body.1562.preheader: ; preds = %do.body124.1, %do.body90
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%storemerge = phi <4 x i32> [ %tmp3, %do.body90 ], [ %tmp7, %do.body124.1 ]
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%tmp4 = insertelement <4 x i32> undef, i32 undef, i32 1
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br label %for.inc.1
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do.body56.1: ; preds = %do.body.preheader
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%tmp5 = insertelement <4 x i32> %tmp, i32 undef, i32 1
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%or.cond472.1 = or i1 undef, undef
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br i1 %or.cond472.1, label %do.body56.2, label %do.body90
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do.body56.2: ; preds = %do.body56.1
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%tmp6 = insertelement <4 x i32> %tmp5, i32 undef, i32 1
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br label %do.body90
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do.body124.1: ; preds = %do.body90
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%tmp7 = insertelement <4 x i32> %tmp3, i32 undef, i32 3
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br label %do.body.1562.preheader
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for.inc.1: ; preds = %do.body.1562.preheader, %entry
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%storemerge591 = phi <4 x i32> [ zeroinitializer, %entry ], [ %storemerge, %do.body.1562.preheader ]
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%add.i495 = add <4 x i32> %storemerge591, undef
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unreachable
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}
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; GCN-LABEL: {{^}}foo:
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; GCN: s_endpgm
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define amdgpu_ps void @foo() #0 {
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bb:
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br i1 undef, label %bb2, label %bb1
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bb1: ; preds = %bb
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br i1 undef, label %bb4, label %bb6
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bb2: ; preds = %bb4, %bb
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%tmp = phi float [ %tmp5, %bb4 ], [ 0.000000e+00, %bb ]
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br i1 undef, label %bb9, label %bb13
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bb4: ; preds = %bb7, %bb6, %bb1
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%tmp5 = phi float [ undef, %bb1 ], [ undef, %bb6 ], [ %tmp8, %bb7 ]
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br label %bb2
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bb6: ; preds = %bb1
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br i1 undef, label %bb7, label %bb4
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bb7: ; preds = %bb6
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%tmp8 = fmul float undef, undef
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br label %bb4
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bb9: ; preds = %bb2
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%tmp10 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
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%tmp11 = extractelement <4 x float> %tmp10, i32 1
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%tmp12 = extractelement <4 x float> %tmp10, i32 3
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br label %bb14
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bb13: ; preds = %bb2
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br i1 undef, label %bb23, label %bb24
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bb14: ; preds = %bb27, %bb24, %bb9
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%tmp15 = phi float [ %tmp12, %bb9 ], [ undef, %bb27 ], [ 0.000000e+00, %bb24 ]
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%tmp16 = phi float [ %tmp11, %bb9 ], [ undef, %bb27 ], [ %tmp25, %bb24 ]
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%tmp17 = fmul float 1.050000e+01, %tmp16
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%tmp18 = fmul float 1.150000e+01, %tmp15
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp18, float %tmp17, float %tmp17, float %tmp17, i1 true, i1 true) #0
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ret void
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bb23: ; preds = %bb13
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br i1 undef, label %bb24, label %bb26
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bb24: ; preds = %bb26, %bb23, %bb13
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%tmp25 = phi float [ %tmp, %bb13 ], [ %tmp, %bb26 ], [ 0.000000e+00, %bb23 ]
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br i1 undef, label %bb27, label %bb14
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bb26: ; preds = %bb23
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br label %bb24
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bb27: ; preds = %bb24
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br label %bb14
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}
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declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
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declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readonly }
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