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196e7f3138
Replace individual operands GLC, SLC, and DLC with a single cache_policy bitmask operand. This will reduce the number of operands in MIR and I hope the amount of code. These operands are mostly 0 anyway. Additional advantage that parser will accept these flags in any order unlike now. Differential Revision: https://reviews.llvm.org/D96469
37 lines
1.2 KiB
YAML
37 lines
1.2 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=gfx1010 -start-before=greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
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...
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# GCN-LABEL: {{^}}"subvector-basic-bb"
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# GCN: s_subvector_loop_begin [[RS:s[0-9]]], BB0_2
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# GCN: s_subvector_loop_end [[RS]], BB0_1
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name: subvector-basic-bb
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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frameOffsetReg: $sgpr5
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stackPtrOffsetReg: $sgpr32
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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successors: %bb.1, %bb.2
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%1:sgpr_64 = COPY $sgpr0_sgpr1
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%4:sgpr_128 = S_LOAD_DWORDX4_IMM %1, 36, 0
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%11:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4.sub2_sub3, 0, 0
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undef %15.sub0:vreg_64 = COPY %4.sub0
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%15.sub1:vreg_64 = COPY %4.sub1
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%16:vgpr_32 = COPY %1.sub0
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S_SUBVECTOR_LOOP_BEGIN %bb.2, undef %19:sreg_32, implicit-def $exec, implicit $exec, implicit-def %19
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bb.1:
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successors: %bb.1, %bb.2
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%14:sreg_32_xm0 = S_ADD_I32 %11.sub0, %11.sub1, implicit-def dead $scc
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%16:vgpr_32 = COPY %14
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S_SUBVECTOR_LOOP_END %bb.1, %19:sreg_32, implicit-def $exec, implicit $exec, implicit-def %19
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bb.2:
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GLOBAL_STORE_DWORD %15, %16, 0, 0, implicit $exec
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S_ENDPGM 0
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...
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