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ccb53c0a97
Treat a non-atomic volatile load and store as a relaxed atomic at system scope for the address spaces accessed. This will ensure all relevant caches will be bypassed. A volatile atomic is not changed and still only bypasses caches upto the level specified by the SyncScope operand. Differential Revision: https://reviews.llvm.org/D94214
161 lines
5.5 KiB
LLVM
161 lines
5.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tahiti -verify-machineinstrs | FileCheck %s --check-prefix=SI
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; RUN: llc < %s -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=VI
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define amdgpu_kernel void @madak_f16(
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; SI-LABEL: madak_f16:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_mov_b32 s10, s2
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; SI-NEXT: s_mov_b32 s11, s3
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b32 s12, s6
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; SI-NEXT: s_mov_b32 s13, s7
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; SI-NEXT: s_mov_b32 s14, s2
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; SI-NEXT: s_mov_b32 s15, s3
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; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
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; SI-NEXT: buffer_load_ushort v1, off, s[12:15], 0
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; SI-NEXT: s_mov_b32 s0, s4
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; SI-NEXT: s_mov_b32 s1, s5
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; SI-NEXT: s_waitcnt vmcnt(1)
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; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
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; SI-NEXT: v_madak_f32 v0, v1, v0, 0x41200000
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; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
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; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: madak_f16:
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; VI: ; %bb.0: ; %entry
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; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: s_mov_b32 s10, s2
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_mov_b32 s0, s4
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; VI-NEXT: s_mov_b32 s1, s5
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; VI-NEXT: s_mov_b32 s4, s6
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; VI-NEXT: s_mov_b32 s5, s7
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; VI-NEXT: s_mov_b32 s6, s2
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; VI-NEXT: s_mov_b32 s7, s3
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; VI-NEXT: s_mov_b32 s11, s3
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; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
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; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_madak_f16 v0, v0, v1, 0x4900
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; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
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; VI-NEXT: s_endpgm
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half addrspace(1)* %r,
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half addrspace(1)* %a,
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half addrspace(1)* %b) #0 {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%b.val = load half, half addrspace(1)* %b
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%t.val = fmul half %a.val, %b.val
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%r.val = fadd half %t.val, 10.0
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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define amdgpu_kernel void @madak_f16_use_2(
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; SI-LABEL: madak_f16_use_2:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x9
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; SI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x11
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_mov_b32 s18, s2
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b32 s16, s8
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; SI-NEXT: s_mov_b32 s17, s9
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; SI-NEXT: s_mov_b32 s19, s3
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; SI-NEXT: s_mov_b32 s8, s10
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; SI-NEXT: s_mov_b32 s9, s11
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; SI-NEXT: s_mov_b32 s10, s2
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; SI-NEXT: s_mov_b32 s11, s3
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; SI-NEXT: s_mov_b32 s14, s2
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; SI-NEXT: s_mov_b32 s15, s3
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; SI-NEXT: buffer_load_ushort v0, off, s[16:19], 0 glc
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 glc
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: buffer_load_ushort v2, off, s[12:15], 0 glc
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_mov_b32_e32 v3, 0x41200000
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; SI-NEXT: s_mov_b32 s0, s4
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; SI-NEXT: s_mov_b32 s1, s5
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; SI-NEXT: s_mov_b32 s8, s6
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; SI-NEXT: s_mov_b32 s9, s7
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; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
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; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
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; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
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; SI-NEXT: v_madak_f32 v1, v0, v1, 0x41200000
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; SI-NEXT: v_mac_f32_e32 v3, v0, v2
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; SI-NEXT: v_cvt_f16_f32_e32 v0, v1
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; SI-NEXT: v_cvt_f16_f32_e32 v1, v3
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; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
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; SI-NEXT: buffer_store_short v1, off, s[8:11], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: madak_f16_use_2:
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; VI: ; %bb.0: ; %entry
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; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
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; VI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x44
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: s_mov_b32 s18, s2
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_mov_b32 s16, s8
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; VI-NEXT: s_mov_b32 s17, s9
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; VI-NEXT: s_mov_b32 s19, s3
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; VI-NEXT: s_mov_b32 s8, s10
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; VI-NEXT: s_mov_b32 s9, s11
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; VI-NEXT: s_mov_b32 s10, s2
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; VI-NEXT: s_mov_b32 s11, s3
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; VI-NEXT: s_mov_b32 s14, s2
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; VI-NEXT: s_mov_b32 s15, s3
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; VI-NEXT: buffer_load_ushort v0, off, s[16:19], 0 glc
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 glc
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: buffer_load_ushort v2, off, s[12:15], 0 glc
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v3, 0x4900
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; VI-NEXT: s_mov_b32 s0, s4
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; VI-NEXT: s_mov_b32 s1, s5
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; VI-NEXT: s_mov_b32 s8, s6
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; VI-NEXT: s_mov_b32 s9, s7
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; VI-NEXT: v_madak_f16 v1, v0, v1, 0x4900
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; VI-NEXT: v_mac_f16_e32 v3, v0, v2
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; VI-NEXT: buffer_store_short v1, off, s[0:3], 0
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; VI-NEXT: buffer_store_short v3, off, s[8:11], 0
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; VI-NEXT: s_endpgm
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half addrspace(1)* %r0,
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half addrspace(1)* %r1,
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half addrspace(1)* %a,
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half addrspace(1)* %b,
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half addrspace(1)* %c) #0 {
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entry:
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%a.val = load volatile half, half addrspace(1)* %a
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%b.val = load volatile half, half addrspace(1)* %b
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%c.val = load volatile half, half addrspace(1)* %c
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%t0.val = fmul half %a.val, %b.val
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%t1.val = fmul half %a.val, %c.val
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%r0.val = fadd half %t0.val, 10.0
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%r1.val = fadd half %t1.val, 10.0
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store half %r0.val, half addrspace(1)* %r0
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store half %r1.val, half addrspace(1)* %r1
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ret void
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}
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attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" }
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