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https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-26 04:32:44 +01:00
bbf5be9d55
This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
298 lines
8.8 KiB
YAML
298 lines
8.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple thumbv8m.base-none-eabi -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s
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--- |
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8m.base-none-none-eabi"
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define i32 @test_subrr(i32 %a, i32 %b) { ret i32 %a }
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define i32 @test_subrr_c(i32 %a, i32 %b) { ret i32 %a }
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define i32 @test_subri3(i32 %a) { ret i32 %a }
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define i32 @test_subri8(i32 %a) { ret i32 %a }
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define i32 @test_addrr(i32 %a) { ret i32 %a }
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define i32 @test_addri3(i32 %a) { ret i32 %a }
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define i32 @test_addri8(i32 %a) { ret i32 %a }
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...
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---
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name: test_subrr
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liveins:
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- { reg: '$r0', virtual-reg: '%1' }
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- { reg: '$r1', virtual-reg: '%2' }
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body: |
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; CHECK-LABEL: name: test_subrr
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; CHECK: bb.0:
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; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
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; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: %2:tgpr, $cpsr = tSUBrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
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; CHECK: tBcc %bb.2, 8 /* CC::hi */, $cpsr
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; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
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; CHECK: bb.1:
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; CHECK: $r0 = COPY %2
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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; CHECK: bb.2:
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; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
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; CHECK: $r0 = COPY %3
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0, $r1
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%2:tgpr = COPY $r1
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%1:tgpr = COPY $r0
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%0:tgpr, $cpsr = tSUBrr %2, %1, 14, $noreg
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tCMPr %1, %2, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 3, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%3:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %3
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_subrr_c
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liveins:
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- { reg: '$r0', virtual-reg: '%1' }
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- { reg: '$r1', virtual-reg: '%2' }
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body: |
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; CHECK-LABEL: name: test_subrr_c
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; CHECK: bb.0:
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; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
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; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: %2:tgpr, $cpsr = tSUBrr [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg
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; CHECK: tBcc %bb.2, 3 /* CC::lo */, $cpsr
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; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
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; CHECK: bb.1:
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; CHECK: $r0 = COPY %2
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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; CHECK: bb.2:
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; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
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; CHECK: $r0 = COPY %3
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0, $r1
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%2:tgpr = COPY $r1
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%1:tgpr = COPY $r0
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%0:tgpr, $cpsr = tSUBrr %1, %2, 14, $noreg
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tCMPr %1, %2, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 3, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%3:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %3
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_subri3
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liveins:
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- { reg: '$r0', virtual-reg: '%1' }
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body: |
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; CHECK-LABEL: name: test_subri3
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; CHECK: bb.0:
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; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: %1:tgpr, $cpsr = tSUBi3 [[COPY]], 1, 14 /* CC::al */, $noreg
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; CHECK: tBcc %bb.2, 3 /* CC::lo */, $cpsr
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; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
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; CHECK: bb.1:
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; CHECK: $r0 = COPY %1
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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; CHECK: bb.2:
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; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
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; CHECK: $r0 = COPY %2
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0
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%1:tgpr = COPY $r0
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%0:tgpr, $cpsr = tSUBi3 %1, 1, 14, $noreg
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tCMPi8 %1, 1, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 3, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_subri8
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liveins:
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- { reg: '$r0', virtual-reg: '%1' }
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body: |
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; CHECK-LABEL: name: test_subri8
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; CHECK: bb.0:
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; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: %1:tgpr, $cpsr = tSUBi8 [[COPY]], 1, 14 /* CC::al */, $noreg
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; CHECK: tBcc %bb.2, 3 /* CC::lo */, $cpsr
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; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
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; CHECK: bb.1:
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; CHECK: $r0 = COPY %1
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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; CHECK: bb.2:
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; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
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; CHECK: $r0 = COPY %2
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0
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%1:tgpr = COPY $r0
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%0:tgpr, $cpsr = tSUBi8 %1, 1, 14, $noreg
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tCMPi8 %1, 1, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 3, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_addrr
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liveins:
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- { reg: '$r0', virtual-reg: '%1' }
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- { reg: '$r1', virtual-reg: '%2' }
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body: |
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; CHECK-LABEL: name: test_addrr
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; CHECK: bb.0:
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; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
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; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: %2:tgpr, $cpsr = tADDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
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; CHECK: tBcc %bb.2, 2 /* CC::hs */, $cpsr
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; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
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; CHECK: bb.1:
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; CHECK: $r0 = COPY %2
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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; CHECK: bb.2:
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; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
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; CHECK: $r0 = COPY %3
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0, $r1
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%2:tgpr = COPY $r1
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%1:tgpr = COPY $r0
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%0:tgpr, $cpsr = tADDrr %2, %1, 14, $noreg
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tCMPr %0, %2, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 3, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%3:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %3
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_addri3
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liveins:
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- { reg: '$r0', virtual-reg: '%1' }
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body: |
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; CHECK-LABEL: name: test_addri3
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; CHECK: bb.0:
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; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: %0:tgpr, $cpsr = tADDi3 [[COPY]], 1, 14 /* CC::al */, $noreg
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; CHECK: tBcc %bb.2, 2 /* CC::hs */, $cpsr
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; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
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; CHECK: bb.1:
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; CHECK: $r0 = COPY [[COPY]]
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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; CHECK: bb.2:
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; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
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; CHECK: $r0 = COPY %2
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0
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%0:tgpr = COPY $r0
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%1:tgpr, $cpsr = tADDi3 %0, 1, 14, $noreg
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tCMPr %1, %0, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 3, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_addri8
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liveins:
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- { reg: '$r0', virtual-reg: '%1' }
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body: |
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; CHECK-LABEL: name: test_addri8
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; CHECK: bb.0:
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; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: %0:tgpr, $cpsr = tADDi8 [[COPY]], 10, 14 /* CC::al */, $noreg
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; CHECK: tBcc %bb.2, 2 /* CC::hs */, $cpsr
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; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
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; CHECK: bb.1:
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; CHECK: $r0 = COPY [[COPY]]
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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; CHECK: bb.2:
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; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
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; CHECK: $r0 = COPY %2
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0
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%0:tgpr = COPY $r0
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%1:tgpr, $cpsr = tADDi8 %0, 10, 14, $noreg
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tCMPr %1, %0, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 3, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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...
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