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44ebb7579c
This is based on the assumption that most simulated instructions don't define more than one or two registers. This is true for example on x86, where most instruction definitions don't declare more than one register write. The default code region size has been increased from 8 to 16. This is based on the assumption that, for small microbenchmarks, the typical code snippet size is often less than 16 instructions. mca::Instruction now uses bitfields to pack flags. No functional change intended.
37 lines
1.1 KiB
C++
37 lines
1.1 KiB
C++
//===--------------------- CodeEmitter.cpp ----------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the CodeEmitter API.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/MCA/CodeEmitter.h"
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namespace llvm {
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namespace mca {
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CodeEmitter::EncodingInfo CodeEmitter::getOrCreateEncodingInfo(unsigned MCID) {
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EncodingInfo &EI = Encodings[MCID];
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if (EI.second)
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return EI;
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SmallVector<llvm::MCFixup, 2> Fixups;
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const MCInst &Inst = Sequence[MCID];
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MCInst Relaxed(Sequence[MCID]);
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if (MAB.mayNeedRelaxation(Inst, STI))
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MAB.relaxInstruction(Relaxed, STI);
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EI.first = Code.size();
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MCE.encodeInstruction(Relaxed, VecOS, Fixups, STI);
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EI.second = Code.size() - EI.first;
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return EI;
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}
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} // namespace mca
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} // namespace llvm
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