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bc7384fc93
Introduce new versions that follow the IEEE semantics to help with legalization that may need quieted inputs. There are some regressions from inserting unnecessary canonicalizes when these are matched from fast math fcmp + select which should be fixed in a future commit. llvm-svn: 344914
28 lines
1.6 KiB
LLVM
28 lines
1.6 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare double @llvm.maxnum.f64(double, double) nounwind readnone
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; SI-LABEL: {{^}}test_fmax3_f64:
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; SI: buffer_load_dwordx2 [[REGA:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0{{$}}
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; SI: buffer_load_dwordx2 [[REGB:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:8
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; SI: buffer_load_dwordx2 [[REGC:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:16
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; SI: v_max_f64 [[QUIET_A:v\[[0-9]+:[0-9]+\]]], [[REGA]], [[REGA]]
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; SI: v_max_f64 [[QUIET_B:v\[[0-9]+:[0-9]+\]]], [[REGB]], [[REGB]]
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; SI: v_max_f64 [[MAX0:v\[[0-9]+:[0-9]+\]]], [[QUIET_A]], [[QUIET_B]]
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; SI: v_max_f64 [[QUIET_C:v\[[0-9]+:[0-9]+\]]], [[REGC]], [[REGC]]
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; SI: v_max_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[MAX0]], [[QUIET_C]]
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; SI: buffer_store_dwordx2 [[RESULT]],
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; SI: s_endpgm
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define amdgpu_kernel void @test_fmax3_f64(double addrspace(1)* %out, double addrspace(1)* %aptr) nounwind {
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%bptr = getelementptr double, double addrspace(1)* %aptr, i32 1
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%cptr = getelementptr double, double addrspace(1)* %aptr, i32 2
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%a = load volatile double, double addrspace(1)* %aptr, align 8
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%b = load volatile double, double addrspace(1)* %bptr, align 8
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%c = load volatile double, double addrspace(1)* %cptr, align 8
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%f0 = call double @llvm.maxnum.f64(double %a, double %b) nounwind readnone
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%f1 = call double @llvm.maxnum.f64(double %f0, double %c) nounwind readnone
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store double %f1, double addrspace(1)* %out, align 8
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ret void
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}
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