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3c906070f5
Literal encoding needs op_sel_hi to select low 16 bit in this case. Differential Revision: https://reviews.llvm.org/D45745 llvm-svn: 330230
108 lines
6.3 KiB
LLVM
108 lines
6.3 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-fp64-fp16-denormals -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,GFX9-FLUSH,GFX9 %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-fp64-fp16-denormals -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,GFX9-FLUSH,GFX9 %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-fp64-fp16-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,GFX9-FLUSH,GFX9 %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-fp64-fp16-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,GFX9-FLUSH,GFX9 %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=+fp64-fp16-denormals -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,GFX9-DENORM-STRICT,GFX9-DENORM,GFX9 %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=+fp64-fp16-denormals -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,GFX9-DENORM-STRICT,GFX9-DENORM,GFX9 %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=+fp64-fp16-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,GFX9-DENORM-CONTRACT,GFX9-DENORM,GFX9 %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=+fp64-fp16-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,GFX9-DENORM-CONTRACT,GFX9-DENORM,GFX9 %s
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare <2 x half> @llvm.fmuladd.v2f16(<2 x half>, <2 x half>, <2 x half>) #1
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declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #1
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; GCN-LABEL: {{^}}fmuladd_v2f16:
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; GFX9-FLUSH: v_pk_mul_f16 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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; GFX9-FLUSH: v_pk_add_f16 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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; GFX9-DENORM: v_pk_fma_f16 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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define amdgpu_kernel void @fmuladd_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in1,
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<2 x half> addrspace(1)* %in2, <2 x half> addrspace(1)* %in3) #0 {
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%r0 = load <2 x half>, <2 x half> addrspace(1)* %in1
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%r1 = load <2 x half>, <2 x half> addrspace(1)* %in2
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%r2 = load <2 x half>, <2 x half> addrspace(1)* %in3
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%r3 = tail call <2 x half> @llvm.fmuladd.v2f16(<2 x half> %r0, <2 x half> %r1, <2 x half> %r2)
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store <2 x half> %r3, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}fmuladd_2.0_a_b_v2f16:
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; GCN: {{buffer|flat|global}}_load_dword [[R1:v[0-9]+]],
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; GCN: {{buffer|flat|global}}_load_dword [[R2:v[0-9]+]],
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; GFX9-FLUSH: v_pk_add_f16 [[ADD0:v[0-9]+]], [[R1]], [[R1]]
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; GFX9-FLUSH: v_pk_add_f16 [[RESULT:v[0-9]+]], [[ADD0]], [[R2]]
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; GFX9-FLUSH: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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; GFX9-DENORM: v_pk_fma_f16 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]]
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; GFX9-DENORM: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @fmuladd_2.0_a_b_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.0 = getelementptr <2 x half>, <2 x half> addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr <2 x half>, <2 x half> addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr <2 x half>, <2 x half> addrspace(1)* %out, i32 %tid
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%r1 = load volatile <2 x half>, <2 x half> addrspace(1)* %gep.0
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%r2 = load volatile <2 x half>, <2 x half> addrspace(1)* %gep.1
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%r3 = tail call <2 x half> @llvm.fmuladd.v2f16(<2 x half> <half 2.0, half 2.0>, <2 x half> %r1, <2 x half> %r2)
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store <2 x half> %r3, <2 x half> addrspace(1)* %gep.out
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ret void
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}
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; GCN-LABEL: {{^}}fmuladd_a_2.0_b_v2f16:
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; GCN: {{buffer|flat|global}}_load_dword [[R1:v[0-9]+]],
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; GCN: {{buffer|flat|global}}_load_dword [[R2:v[0-9]+]],
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; GFX9-FLUSH: v_pk_add_f16 [[ADD0:v[0-9]+]], [[R1]], [[R1]]
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; GFX9-FLUSH: v_pk_add_f16 [[RESULT:v[0-9]+]], [[ADD0]], [[R2]]
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; GFX9-FLUSH: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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; GFX9-DENORM: v_pk_fma_f16 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]]
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; GFX9-DENORM: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @fmuladd_a_2.0_b_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.0 = getelementptr <2 x half>, <2 x half> addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr <2 x half>, <2 x half> addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr <2 x half>, <2 x half> addrspace(1)* %out, i32 %tid
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%r1 = load volatile <2 x half>, <2 x half> addrspace(1)* %gep.0
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%r2 = load volatile <2 x half>, <2 x half> addrspace(1)* %gep.1
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%r3 = tail call <2 x half> @llvm.fmuladd.v2f16(<2 x half> %r1, <2 x half> <half 2.0, half 2.0>, <2 x half> %r2)
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store <2 x half> %r3, <2 x half> addrspace(1)* %gep.out
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ret void
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}
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; GCN-LABEL: {{^}}fadd_a_a_b_v2f16:
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; GCN: {{buffer|flat|global}}_load_dword [[R1:v[0-9]+]],
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; GCN: {{buffer|flat|global}}_load_dword [[R2:v[0-9]+]],
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; GFX9-FLUSH: v_pk_add_f16 [[ADD0:v[0-9]+]], [[R1]], [[R1]]
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; GFX9-FLUSH: v_pk_add_f16 [[RESULT:v[0-9]+]], [[ADD0]], [[R2]]
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; GFX9-DENORM-STRICT: v_pk_add_f16 [[ADD0:v[0-9]+]], [[R1]], [[R1]]
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; GFX9-DENORM-STRICT: v_pk_add_f16 [[RESULT:v[0-9]+]], [[ADD0]], [[R2]]
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; GFX9-DENORM-CONTRACT: v_pk_fma_f16 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]]
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; GCN: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @fadd_a_a_b_v2f16(<2 x half> addrspace(1)* %out,
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<2 x half> addrspace(1)* %in1,
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<2 x half> addrspace(1)* %in2) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.0 = getelementptr <2 x half>, <2 x half> addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr <2 x half>, <2 x half> addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr <2 x half>, <2 x half> addrspace(1)* %out, i32 %tid
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%r0 = load volatile <2 x half>, <2 x half> addrspace(1)* %gep.0
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%r1 = load volatile <2 x half>, <2 x half> addrspace(1)* %gep.1
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%add.0 = fadd <2 x half> %r0, %r0
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%add.1 = fadd <2 x half> %add.0, %r1
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store <2 x half> %add.1, <2 x half> addrspace(1)* %gep.out
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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