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ea47e86cdc
Summary: To workaround a hardware issue in the (base + offset) calculation when base is negative. The impact on code quality should be limited since SILoadStoreOptimizer still runs afterwards and is able to combine loads/stores based on known sign information. This fixes visible corruption in Hitman on SI (easily reproducible by running benchmark mode). Change-Id: Ia178d207a5e2ac38ae7cd98b532ea2ae74704e5f Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99923 Reviewers: arsenm, mareko Subscribers: jholewinski, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D53160 llvm-svn: 344698
130 lines
4.0 KiB
LLVM
130 lines
4.0 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s
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; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NOSI %s
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@compute_lds = external addrspace(3) global [512 x i32], align 16
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; GCN-LABEL: {{^}}store_aligned:
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; GCN: ds_write_b64
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define amdgpu_cs void @store_aligned(i32 addrspace(3)* %ptr) #0 {
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entry:
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%ptr.gep.1 = getelementptr i32, i32 addrspace(3)* %ptr, i32 1
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store i32 42, i32 addrspace(3)* %ptr, align 8
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store i32 43, i32 addrspace(3)* %ptr.gep.1
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ret void
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}
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; GCN-LABEL: {{^}}load_aligned:
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; GCN: ds_read_b64
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define amdgpu_cs <2 x float> @load_aligned(i32 addrspace(3)* %ptr) #0 {
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entry:
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%ptr.gep.1 = getelementptr i32, i32 addrspace(3)* %ptr, i32 1
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%v.0 = load i32, i32 addrspace(3)* %ptr, align 8
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%v.1 = load i32, i32 addrspace(3)* %ptr.gep.1
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%r.0 = insertelement <2 x i32> undef, i32 %v.0, i32 0
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%r.1 = insertelement <2 x i32> %r.0, i32 %v.1, i32 1
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%bc = bitcast <2 x i32> %r.1 to <2 x float>
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ret <2 x float> %bc
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}
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; GCN-LABEL: {{^}}store_global_const_idx:
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; GCN: ds_write2_b32
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define amdgpu_cs void @store_global_const_idx() #0 {
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entry:
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%ptr.a = getelementptr [512 x i32], [512 x i32] addrspace(3)* @compute_lds, i32 0, i32 3
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%ptr.b = getelementptr [512 x i32], [512 x i32] addrspace(3)* @compute_lds, i32 0, i32 4
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store i32 42, i32 addrspace(3)* %ptr.a
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store i32 43, i32 addrspace(3)* %ptr.b
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ret void
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}
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; GCN-LABEL: {{^}}load_global_const_idx:
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; GCN: ds_read2_b32
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define amdgpu_cs <2 x float> @load_global_const_idx() #0 {
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entry:
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%ptr.a = getelementptr [512 x i32], [512 x i32] addrspace(3)* @compute_lds, i32 0, i32 3
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%ptr.b = getelementptr [512 x i32], [512 x i32] addrspace(3)* @compute_lds, i32 0, i32 4
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%v.0 = load i32, i32 addrspace(3)* %ptr.a
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%v.1 = load i32, i32 addrspace(3)* %ptr.b
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%r.0 = insertelement <2 x i32> undef, i32 %v.0, i32 0
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%r.1 = insertelement <2 x i32> %r.0, i32 %v.1, i32 1
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%bc = bitcast <2 x i32> %r.1 to <2 x float>
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ret <2 x float> %bc
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}
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; GCN-LABEL: {{^}}store_global_var_idx_case1:
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; SI: ds_write_b32
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; SI: ds_write_b32
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; NONSI: ds_write2_b32
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define amdgpu_cs void @store_global_var_idx_case1(i32 %idx) #0 {
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entry:
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%ptr.a = getelementptr [512 x i32], [512 x i32] addrspace(3)* @compute_lds, i32 0, i32 %idx
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%ptr.b = getelementptr i32, i32 addrspace(3)* %ptr.a, i32 1
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store i32 42, i32 addrspace(3)* %ptr.a
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store i32 43, i32 addrspace(3)* %ptr.b
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ret void
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}
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; GCN-LABEL: {{^}}load_global_var_idx_case1:
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; SI: ds_read_b32
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; SI: ds_read_b32
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; NONSI: ds_read2_b32
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define amdgpu_cs <2 x float> @load_global_var_idx_case1(i32 %idx) #0 {
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entry:
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%ptr.a = getelementptr [512 x i32], [512 x i32] addrspace(3)* @compute_lds, i32 0, i32 %idx
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%ptr.b = getelementptr i32, i32 addrspace(3)* %ptr.a, i32 1
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%v.0 = load i32, i32 addrspace(3)* %ptr.a
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%v.1 = load i32, i32 addrspace(3)* %ptr.b
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%r.0 = insertelement <2 x i32> undef, i32 %v.0, i32 0
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%r.1 = insertelement <2 x i32> %r.0, i32 %v.1, i32 1
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%bc = bitcast <2 x i32> %r.1 to <2 x float>
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ret <2 x float> %bc
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}
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; GCN-LABEL: {{^}}store_global_var_idx_case2:
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; GCN: ds_write2_b32
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define amdgpu_cs void @store_global_var_idx_case2(i32 %idx) #0 {
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entry:
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%idx.and = and i32 %idx, 255
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%ptr.a = getelementptr [512 x i32], [512 x i32] addrspace(3)* @compute_lds, i32 0, i32 %idx.and
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%ptr.b = getelementptr i32, i32 addrspace(3)* %ptr.a, i32 1
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store i32 42, i32 addrspace(3)* %ptr.a
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store i32 43, i32 addrspace(3)* %ptr.b
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ret void
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}
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; GCN-LABEL: {{^}}load_global_var_idx_case2:
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; GCN: ds_read2_b32
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define amdgpu_cs <2 x float> @load_global_var_idx_case2(i32 %idx) #0 {
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entry:
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%idx.and = and i32 %idx, 255
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%ptr.a = getelementptr [512 x i32], [512 x i32] addrspace(3)* @compute_lds, i32 0, i32 %idx.and
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%ptr.b = getelementptr i32, i32 addrspace(3)* %ptr.a, i32 1
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%v.0 = load i32, i32 addrspace(3)* %ptr.a
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%v.1 = load i32, i32 addrspace(3)* %ptr.b
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%r.0 = insertelement <2 x i32> undef, i32 %v.0, i32 0
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%r.1 = insertelement <2 x i32> %r.0, i32 %v.1, i32 1
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%bc = bitcast <2 x i32> %r.1 to <2 x float>
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ret <2 x float> %bc
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}
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attributes #0 = { nounwind }
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