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f58aee7cea
Summary: Also explicitly port over some tests in llvm.amdgcn.image.* that were missing. Some tests are removed because they no longer apply (i.e. explicitly testing building an address vector via insertelement). This is in preparation for the eventual removal of the old-style intrinsics. Some additional notes: - constant-address-space-32bit.ll: change some GCN-NEXT to GCN because the instruction schedule was subtly altered - insert_vector_elt.ll: the old test didn't actually test anything, because %tmp1 was not used; remove the load, because it doesn't work (Because of the amdgpu_ps calling convention? In any case, it's orthogonal to what the test claims to be testing.) Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf Reviewers: arsenm, rampitec Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D48018 llvm-svn: 335229
41 lines
1.6 KiB
LLVM
41 lines
1.6 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
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; CHECK-LABEL: {{^}}test1:
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; CHECK-NOT: s_waitcnt
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; CHECK: image_store
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0){{$}}
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; CHECK-NEXT: image_store
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test1(<8 x i32> inreg %rsrc, <4 x float> %d0, <4 x float> %d1, i32 %c0, i32 %c1) {
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call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %d0, i32 15, i32 %c0, <8 x i32> %rsrc, i32 0, i32 0)
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call void @llvm.amdgcn.s.waitcnt(i32 3840) ; 0xf00
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call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %d1, i32 15, i32 %c1, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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; Test that the intrinsic is merged with automatically generated waits and
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; emitted as late as possible.
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;
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; CHECK-LABEL: {{^}}test2:
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; CHECK-NOT: s_waitcnt
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; CHECK: image_load
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; CHECK-NEXT: v_lshlrev_b32
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0){{$}}
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; CHECK-NEXT: image_store
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define amdgpu_ps void @test2(<8 x i32> inreg %rsrc, i32 %c) {
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%t = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %c, <8 x i32> %rsrc, i32 0, i32 0)
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call void @llvm.amdgcn.s.waitcnt(i32 3840) ; 0xf00
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%c.1 = mul i32 %c, 2
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call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %t, i32 15, i32 %c.1, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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declare void @llvm.amdgcn.s.waitcnt(i32) #0
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declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32, i32, <8 x i32>, i32, i32) #1
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declare void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float>, i32, i32, <8 x i32>, i32, i32) #0
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readonly }
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