mirror of
https://github.com/RPCS3/llvm-mirror.git
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aee5f0fc5d
- Relex hard coded registers and stack frame sizes - Some test cleanups - Change phi-dbg.ll to match on mir output after phi elimination instead of going through the whole codegen pipeline. This is in preparation for https://reviews.llvm.org/D52010 I'm committing all the test changes upfront that work before and after independently. llvm-svn: 345532
177 lines
5.6 KiB
LLVM
177 lines
5.6 KiB
LLVM
; RUN: llc -O0 -march=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-smem=0 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VGPR %s
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; RUN: llc -O0 -march=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-smem=1 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=SMEM %s
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; RUN: llc -O0 -march=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-smem=0 -amdgpu-spill-sgpr-to-vgpr=0 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VMEM %s
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; ALL-LABEL: {{^}}spill_sgpr_x2:
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; SMEM: s_add_u32 m0, s3, 0x100{{$}}
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; SMEM: s_buffer_store_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[8:11], m0 ; 8-byte Folded Spill
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; SMEM: s_cbranch_scc1
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; SMEM: s_add_u32 m0, s3, 0x100{{$}}
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; SMEM: s_buffer_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[8:11], m0 ; 8-byte Folded Reload
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; SMEM: s_dcache_wb
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; SMEM: s_endpgm
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; FIXME: Should only need 4 bytes
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; SMEM: ScratchSize: 12
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
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; VGPR: s_cbranch_scc1
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: s_cbranch_scc1
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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define amdgpu_kernel void @spill_sgpr_x2(i32 addrspace(1)* %out, i32 %in) #0 {
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%wide.sgpr = call <2 x i32> asm sideeffect "; def $0", "=s" () #0
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%cmp = icmp eq i32 %in, 0
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br i1 %cmp, label %bb0, label %ret
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bb0:
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call void asm sideeffect "; use $0", "s"(<2 x i32> %wide.sgpr) #0
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br label %ret
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ret:
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ret void
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}
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; ALL-LABEL: {{^}}spill_sgpr_x4:
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; SMEM: s_add_u32 m0, s3, 0x100{{$}}
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; SMEM: s_buffer_store_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS:[0-9]+:[0-9]+]]{{\]}}, m0 ; 16-byte Folded Spill
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; SMEM: s_cbranch_scc1
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; SMEM: s_add_u32 m0, s3, 0x100{{$}}
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; SMEM: s_buffer_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS]]{{\]}}, m0 ; 16-byte Folded Reload
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; SMEM: s_dcache_wb
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; SMEM: s_endpgm
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; FIXME: Should only need 4 bytes
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; SMEM: ScratchSize: 20
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3
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; VGPR: s_cbranch_scc1
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: s_cbranch_scc1
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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define amdgpu_kernel void @spill_sgpr_x4(i32 addrspace(1)* %out, i32 %in) #0 {
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%wide.sgpr = call <4 x i32> asm sideeffect "; def $0", "=s" () #0
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%cmp = icmp eq i32 %in, 0
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br i1 %cmp, label %bb0, label %ret
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bb0:
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call void asm sideeffect "; use $0", "s"(<4 x i32> %wide.sgpr) #0
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br label %ret
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ret:
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ret void
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}
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; ALL-LABEL: {{^}}spill_sgpr_x8:
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; SMEM: s_add_u32 m0, s3, 0x100{{$}}
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; SMEM: s_buffer_store_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS:[0-9]+:[0-9]+]]{{\]}}, m0 ; 16-byte Folded Spill
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; SMEM: s_add_u32 m0, s3, 0x110{{$}}
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; SMEM: s_buffer_store_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS]]{{\]}}, m0 ; 16-byte Folded Spill
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; SMEM: s_cbranch_scc1
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; SMEM: s_add_u32 m0, s3, 0x100{{$}}
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; SMEM: s_buffer_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS]]{{\]}}, m0 ; 16-byte Folded Reload
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; SMEM: s_add_u32 m0, s3, 0x110{{$}}
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; SMEM: s_buffer_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS]]{{\]}}, m0 ; 16-byte Folded Reload
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; SMEM: s_dcache_wb
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; SMEM: s_endpgm
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; SMEM: ScratchSize: 36
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 4
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 5
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 6
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 7
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; VGPR: s_cbranch_scc1
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 4
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 5
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 6
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 7
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: s_cbranch_scc1
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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define amdgpu_kernel void @spill_sgpr_x8(i32 addrspace(1)* %out, i32 %in) #0 {
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%wide.sgpr = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
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%cmp = icmp eq i32 %in, 0
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br i1 %cmp, label %bb0, label %ret
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bb0:
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call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr) #0
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br label %ret
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ret:
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ret void
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}
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; FIXME: x16 inlineasm seems broken
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; define amdgpu_kernel void @spill_sgpr_x16(i32 addrspace(1)* %out, i32 %in) #0 {
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; %wide.sgpr = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
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; %cmp = icmp eq i32 %in, 0
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; br i1 %cmp, label %bb0, label %ret
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; bb0:
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; call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr) #0
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; br label %ret
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; ret:
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; ret void
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; }
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attributes #0 = { nounwind }
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