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31c3bd6557
This extends the existing transform for: add X, 0/1 --> sub X, 0/-1 ...to allow the sibling subtraction fold. This pattern could regress with the proposed change in D57401. llvm-svn: 352680
163 lines
5.0 KiB
LLVM
163 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s
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; add (sext i1 X), 1 -> zext (not i1 X)
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define i32 @sext_inc(i1 zeroext %x) nounwind {
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; CHECK-LABEL: sext_inc:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorb $1, %dil
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; CHECK-NEXT: movzbl %dil, %eax
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; CHECK-NEXT: retq
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%ext = sext i1 %x to i32
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%add = add i32 %ext, 1
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ret i32 %add
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}
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; add (sext i1 X), 1 -> zext (not i1 X)
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define <4 x i32> @sext_inc_vec(<4 x i1> %x) nounwind {
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; CHECK-LABEL: sext_inc_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1]
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; CHECK-NEXT: vandnps %xmm1, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%ext = sext <4 x i1> %x to <4 x i32>
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%add = add <4 x i32> %ext, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %add
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}
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define <4 x i32> @cmpgt_sext_inc_vec(<4 x i32> %x, <4 x i32> %y) nounwind {
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; CHECK-LABEL: cmpgt_sext_inc_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
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; CHECK-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1]
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; CHECK-NEXT: vpandn %xmm1, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%cmp = icmp sgt <4 x i32> %x, %y
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%ext = sext <4 x i1> %cmp to <4 x i32>
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%add = add <4 x i32> %ext, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %add
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}
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define <4 x i32> @cmpne_sext_inc_vec(<4 x i32> %x, <4 x i32> %y) nounwind {
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; CHECK-LABEL: cmpne_sext_inc_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
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; CHECK-NEXT: vpsrld $31, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%cmp = icmp ne <4 x i32> %x, %y
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%ext = sext <4 x i1> %cmp to <4 x i32>
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%add = add <4 x i32> %ext, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %add
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}
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define <4 x i64> @cmpgt_sext_inc_vec256(<4 x i64> %x, <4 x i64> %y) nounwind {
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; CHECK-LABEL: cmpgt_sext_inc_vec256:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
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; CHECK-NEXT: vpbroadcastq {{.*#+}} ymm1 = [1,1,1,1]
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; CHECK-NEXT: vpandn %ymm1, %ymm0, %ymm0
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; CHECK-NEXT: retq
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%cmp = icmp sgt <4 x i64> %x, %y
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%ext = sext <4 x i1> %cmp to <4 x i64>
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%add = add <4 x i64> %ext, <i64 1, i64 1, i64 1, i64 1>
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ret <4 x i64> %add
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}
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define i32 @bool_logic_and_math(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; CHECK-LABEL: bool_logic_and_math:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmpl %esi, %edi
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: cmpl %ecx, %edx
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; CHECK-NEXT: sete %cl
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; CHECK-NEXT: orb %al, %cl
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; CHECK-NEXT: movzbl %cl, %eax
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; CHECK-NEXT: retq
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%cmp1 = icmp ne i32 %a, %b
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%cmp2 = icmp ne i32 %c, %d
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%and = and i1 %cmp1, %cmp2
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%ext = sext i1 %and to i32
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%add = add i32 %ext, 1
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ret i32 %add
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}
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define <4 x i32> @bool_logic_and_math_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) nounwind {
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; CHECK-LABEL: bool_logic_and_math_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
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; CHECK-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm1
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; CHECK-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
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; CHECK-NEXT: vpxor %xmm2, %xmm1, %xmm1
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; CHECK-NEXT: vpandn %xmm1, %xmm0, %xmm0
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; CHECK-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1]
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; CHECK-NEXT: vpandn %xmm1, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%cmp1 = icmp ne <4 x i32> %a, %b
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%cmp2 = icmp ne <4 x i32> %c, %d
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%and = and <4 x i1> %cmp1, %cmp2
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%ext = sext <4 x i1> %and to <4 x i32>
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%add = add <4 x i32> %ext, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %add
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}
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define <4 x i32> @sextbool_add_vector(<4 x i32> %cmp1, <4 x i32> %cmp2, <4 x i32> %x) {
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; CHECK-LABEL: sextbool_add_vector:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
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; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0
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; CHECK-NEXT: retq
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%c = icmp eq <4 x i32> %cmp1, %cmp2
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%b = sext <4 x i1> %c to <4 x i32>
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%s = add <4 x i32> %x, %b
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ret <4 x i32> %s
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}
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define <4 x i32> @zextbool_sub_vector(<4 x i32> %cmp1, <4 x i32> %cmp2, <4 x i32> %x) {
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; CHECK-LABEL: zextbool_sub_vector:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
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; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0
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; CHECK-NEXT: retq
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%c = icmp eq <4 x i32> %cmp1, %cmp2
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%b = zext <4 x i1> %c to <4 x i32>
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%s = sub <4 x i32> %x, %b
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ret <4 x i32> %s
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}
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define i32 @assertsext_sub_1(i1 signext %cond, i32 %y) {
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; CHECK-LABEL: assertsext_sub_1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: leal (%rdi,%rsi), %eax
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; CHECK-NEXT: retq
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%e = zext i1 %cond to i32
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%r = sub i32 %y, %e
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ret i32 %r
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}
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define i32 @assertsext_add_1(i1 signext %cond, i32 %y) {
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; CHECK-LABEL: assertsext_add_1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: subl %edi, %eax
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; CHECK-NEXT: retq
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%e = zext i1 %cond to i32
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%r = add i32 %e, %y
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ret i32 %r
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}
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define i32 @assertsext_add_1_commute(i1 signext %cond, i32 %y) {
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; CHECK-LABEL: assertsext_add_1_commute:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: subl %edi, %eax
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; CHECK-NEXT: retq
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%e = zext i1 %cond to i32
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%r = add i32 %y, %e
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ret i32 %r
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}
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