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43dcc4cc5f
MULX has somewhat improved register allocation constraints compared to the legacy MUL instruction. Both output registers are encoded instead of fixed to EAX/EDX, but EDX is used as input. It also doesn't touch flags. Unfortunately, the encoding is longer. Prefering it whenever BMI2 is enabled is probably not optimal. Choosing it should somehow be a function of register allocation constraints like converting adds to three address. gcc and icc definitely don't pick MULX by default. Not sure what if any rules they have for using it. Differential Revision: https://reviews.llvm.org/D55565 llvm-svn: 348975
30 lines
818 B
LLVM
30 lines
818 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+bmi2 | FileCheck %s
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; RUN: llc < %s -mtriple=i686-unknown -mcpu=core-avx2 | FileCheck %s
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define i64 @f1(i32 %a, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: mull {{[0-9]+}}(%esp)
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; CHECK-NEXT: retl
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%x = zext i32 %a to i64
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%y = zext i32 %b to i64
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%r = mul i64 %x, %y
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ret i64 %r
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}
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define i64 @f2(i32 %a, i32* %p) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: mull (%ecx)
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; CHECK-NEXT: retl
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%b = load i32, i32* %p
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%x = zext i32 %a to i64
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%y = zext i32 %b to i64
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%r = mul i64 %x, %y
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ret i64 %r
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}
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