mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-22 12:33:33 +02:00
b0339a1fda
Unlike other v6+ processors, cortex-m0 never supports unaligned accesses. From the v6m ARM ARM: "A3.2 Alignment support: ARMv6-M always generates a fault when an unaligned access occurs." rdar://16491560 llvm-svn: 205452
14 lines
369 B
LLVM
14 lines
369 B
LLVM
; RUN: llc -mtriple=thumbv6m-apple-unknown-macho < %s | FileCheck --check-prefix=V6M %s
|
|
; RUN: llc -mtriple=thumbv7m-apple-unknown-macho < %s | FileCheck --check-prefix=V7M %s
|
|
|
|
define i32 @split_load(i32* %p) nounwind {
|
|
; V6M-LABEL: split_load
|
|
; V6M: ldrh
|
|
; V6M: ldrh
|
|
; V7M-LABEL: split_load
|
|
; V7M-NOT: ldrh
|
|
; V7M: bx lr
|
|
%val = load i32* %p, align 2
|
|
ret i32 %val
|
|
}
|