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01d033c489
This patch adds the ability to describe properties of the hardware retire control unit. Tablegen class RetireControlUnit has been added for this purpose (see TargetSchedule.td). A RetireControlUnit specifies the size of the reorder buffer, as well as the maximum number of opcodes that can be retired every cycle. A zero (or negative) value for the reorder buffer size means: "the size is unknown". If the size is unknown, then llvm-mca defaults it to the value of field SchedMachineModel::MicroOpBufferSize. A zero or negative number of opcodes retired per cycle means: "there is no restriction on the number of instructions that can be retired every cycle". Models can optionally specify an instance of RetireControlUnit. There can only be up-to one RetireControlUnit definition per scheduling model. Information related to the RCU (RetireControlUnit) is stored in (two new fields of) MCExtraProcessorInfo. llvm-mca loads that information when it initializes the DispatchUnit / RetireControlUnit (see Dispatch.h/Dispatch.cpp). This patch fixes PR36661. Differential Revision: https://reviews.llvm.org/D45259 llvm-svn: 329304
103 lines
3.7 KiB
C++
103 lines
3.7 KiB
C++
//===--------------------- Backend.h ----------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file implements an OoO backend for the llvm-mca tool.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TOOLS_LLVM_MCA_BACKEND_H
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#define LLVM_TOOLS_LLVM_MCA_BACKEND_H
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#include "Dispatch.h"
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#include "InstrBuilder.h"
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#include "Scheduler.h"
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#include "SourceMgr.h"
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namespace mca {
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class HWEventListener;
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class HWInstructionEvent;
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class HWStallEvent;
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/// \brief An out of order backend for a specific subtarget.
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///
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/// It emulates an out-of-order execution of instructions. Instructions are
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/// fetched from a MCInst sequence managed by an object of class SourceMgr.
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/// Instructions are firstly dispatched to the schedulers and then executed.
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/// This class tracks the lifetime of an instruction from the moment where
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/// it gets dispatched to the schedulers, to the moment where it finishes
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/// executing and register writes are architecturally committed.
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/// In particular, it monitors changes in the state of every instruction
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/// in flight.
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/// Instructions are executed in a loop of iterations. The number of iterations
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/// is defined by the SourceMgr object.
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/// The Backend entrypoint is method 'Run()' which execute cycles in a loop
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/// until there are new instructions to dispatch, and not every instruction
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/// has been retired.
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/// Internally, the Backend collects statistical information in the form of
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/// histograms. For example, it tracks how the dispatch group size changes
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/// over time.
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class Backend {
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const llvm::MCSubtargetInfo &STI;
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InstrBuilder &IB;
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std::unique_ptr<Scheduler> HWS;
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std::unique_ptr<DispatchUnit> DU;
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SourceMgr &SM;
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unsigned Cycles;
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llvm::DenseMap<unsigned, std::unique_ptr<Instruction>> Instructions;
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std::set<HWEventListener *> Listeners;
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void runCycle(unsigned Cycle);
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public:
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Backend(const llvm::MCSubtargetInfo &Subtarget,
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const llvm::MCRegisterInfo &MRI, InstrBuilder &B, SourceMgr &Source,
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unsigned DispatchWidth = 0, unsigned RegisterFileSize = 0,
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unsigned LoadQueueSize = 0, unsigned StoreQueueSize = 0,
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bool AssumeNoAlias = false)
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: STI(Subtarget), IB(B),
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HWS(llvm::make_unique<Scheduler>(this, Subtarget.getSchedModel(),
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LoadQueueSize, StoreQueueSize,
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AssumeNoAlias)),
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DU(llvm::make_unique<DispatchUnit>(this, Subtarget.getSchedModel(), MRI,
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RegisterFileSize, DispatchWidth,
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HWS.get())),
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SM(Source), Cycles(0) {
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HWS->setDispatchUnit(DU.get());
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}
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void run() {
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while (SM.hasNext() || !DU->isRCUEmpty())
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runCycle(Cycles++);
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}
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const Instruction &getInstruction(unsigned Index) const {
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const auto It = Instructions.find(Index);
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assert(It != Instructions.end() && "no running instructions with index");
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assert(It->second);
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return *It->second;
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}
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void eraseInstruction(unsigned Index) { Instructions.erase(Index); }
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void addEventListener(HWEventListener *Listener);
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void notifyCycleBegin(unsigned Cycle);
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void notifyInstructionEvent(const HWInstructionEvent &Event);
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void notifyStallEvent(const HWStallEvent &Event);
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void notifyResourceAvailable(const ResourceRef &RR);
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void notifyReservedBuffers(llvm::ArrayRef<unsigned> Buffers);
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void notifyReleasedBuffers(llvm::ArrayRef<unsigned> Buffers);
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void notifyCycleEnd(unsigned Cycle);
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};
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} // namespace mca
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#endif
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