mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-02-01 05:01:59 +01:00
abb03b6ae8
This unfortunately requires a bunch of bitcasts to be added added to SUBREG_TO_REG, COPY_TO_REGCLASS, and instructions in output patterns. Otherwise tablegen seems to default to picking f128 and then we fail when something tries to get the register class for f128 which isn't always valid. The test changes are because we were previously mixing fr128 and vr128 due to contrainRegClass finding FR128 first and passes like live range shrinking weren't handling that well. llvm-svn: 337147
860 lines
29 KiB
YAML
860 lines
29 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -run-pass x86-domain-reassignment -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512dq -o - %s | FileCheck %s
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--- |
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; ModuleID = '../test/CodeGen/X86/gpr-to-mask.ll'
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source_filename = "../test/CodeGen/X86/gpr-to-mask.ll"
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-unknown"
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define void @test_fcmp_storefloat(i1 %cond, float* %fptr, float %f1, float %f2, float %f3, float %f4, float %f5, float %f6) #0 {
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entry:
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br i1 %cond, label %if, label %else
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if: ; preds = %entry
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%cmp1 = fcmp oeq float %f3, %f4
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br label %exit
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else: ; preds = %entry
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%cmp2 = fcmp oeq float %f5, %f6
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br label %exit
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exit: ; preds = %else, %if
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%val = phi i1 [ %cmp1, %if ], [ %cmp2, %else ]
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%selected = select i1 %val, float %f1, float %f2
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store float %selected, float* %fptr
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ret void
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}
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define void @test_8bitops() #0 {
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ret void
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}
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define void @test_16bitops() #0 {
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ret void
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}
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define void @test_32bitops() #0 {
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ret void
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}
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define void @test_64bitops() #0 {
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ret void
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}
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define void @test_16bitext() #0 {
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ret void
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}
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define void @test_32bitext() #0 {
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ret void
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}
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define void @test_64bitext() #0 {
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ret void
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}
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...
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---
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name: test_fcmp_storefloat
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr8, preferred-register: '' }
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- { id: 1, class: gr8, preferred-register: '' }
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- { id: 2, class: gr8, preferred-register: '' }
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- { id: 3, class: gr32, preferred-register: '' }
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- { id: 4, class: gr64, preferred-register: '' }
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- { id: 5, class: vr128x, preferred-register: '' }
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- { id: 6, class: fr32x, preferred-register: '' }
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- { id: 7, class: fr32x, preferred-register: '' }
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- { id: 8, class: fr32x, preferred-register: '' }
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- { id: 9, class: fr32x, preferred-register: '' }
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- { id: 10, class: fr32x, preferred-register: '' }
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- { id: 11, class: gr8, preferred-register: '' }
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- { id: 12, class: vk1, preferred-register: '' }
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- { id: 13, class: gr32, preferred-register: '' }
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- { id: 14, class: vk1, preferred-register: '' }
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- { id: 15, class: gr32, preferred-register: '' }
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- { id: 16, class: gr32, preferred-register: '' }
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- { id: 17, class: gr32, preferred-register: '' }
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- { id: 18, class: vk1wm, preferred-register: '' }
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- { id: 19, class: vr128x, preferred-register: '' }
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- { id: 20, class: vr128, preferred-register: '' }
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- { id: 21, class: vr128, preferred-register: '' }
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- { id: 22, class: fr32x, preferred-register: '' }
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liveins:
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- { reg: '$edi', virtual-reg: '%3' }
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- { reg: '$rsi', virtual-reg: '%4' }
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- { reg: '$xmm0', virtual-reg: '%5' }
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- { reg: '$xmm1', virtual-reg: '%6' }
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- { reg: '$xmm2', virtual-reg: '%7' }
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- { reg: '$xmm3', virtual-reg: '%8' }
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- { reg: '$xmm4', virtual-reg: '%9' }
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- { reg: '$xmm5', virtual-reg: '%10' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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; CHECK-LABEL: name: test_fcmp_storefloat
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: liveins: $edi, $rsi, $xmm0, $xmm1, $xmm2, $xmm3, $xmm4, $xmm5
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; CHECK: [[COPY:%[0-9]+]]:fr32x = COPY $xmm5
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; CHECK: [[COPY1:%[0-9]+]]:fr32x = COPY $xmm4
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; CHECK: [[COPY2:%[0-9]+]]:fr32x = COPY $xmm3
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; CHECK: [[COPY3:%[0-9]+]]:fr32x = COPY $xmm2
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; CHECK: [[COPY4:%[0-9]+]]:fr32x = COPY $xmm1
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; CHECK: [[COPY5:%[0-9]+]]:vr128x = COPY $xmm0
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; CHECK: [[COPY6:%[0-9]+]]:gr64 = COPY $rsi
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; CHECK: [[COPY7:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[COPY8:%[0-9]+]]:gr8 = COPY [[COPY7]].sub_8bit
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; CHECK: TEST8ri killed [[COPY8]], 1, implicit-def $eflags
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; CHECK: JE_1 %bb.2, implicit $eflags
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; CHECK: JMP_1 %bb.1
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; CHECK: bb.1.if:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: [[VCMPSSZrr:%[0-9]+]]:vk1 = VCMPSSZrr [[COPY3]], [[COPY2]], 0
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; CHECK: [[COPY9:%[0-9]+]]:vk32 = COPY [[VCMPSSZrr]]
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; CHECK: [[COPY10:%[0-9]+]]:vk8 = COPY [[COPY9]]
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; CHECK: JMP_1 %bb.3
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; CHECK: bb.2.else:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: [[VCMPSSZrr1:%[0-9]+]]:vk1 = VCMPSSZrr [[COPY1]], [[COPY]], 0
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; CHECK: [[COPY11:%[0-9]+]]:vk32 = COPY [[VCMPSSZrr1]]
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; CHECK: [[COPY12:%[0-9]+]]:vk8 = COPY [[COPY11]]
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; CHECK: bb.3.exit:
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; CHECK: [[PHI:%[0-9]+]]:vk8 = PHI [[COPY12]], %bb.2, [[COPY10]], %bb.1
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; CHECK: [[COPY13:%[0-9]+]]:vk32 = COPY [[PHI]]
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; CHECK: [[COPY14:%[0-9]+]]:vk1wm = COPY [[COPY13]]
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; CHECK: [[COPY15:%[0-9]+]]:vr128x = COPY [[COPY4]]
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; CHECK: [[DEF:%[0-9]+]]:vr128 = IMPLICIT_DEF
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; CHECK: [[VMOVSSZrrk:%[0-9]+]]:vr128 = VMOVSSZrrk [[COPY15]], killed [[COPY14]], killed [[DEF]], [[COPY5]]
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; CHECK: [[COPY16:%[0-9]+]]:fr32x = COPY [[VMOVSSZrrk]]
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; CHECK: VMOVSSZmr [[COPY6]], 1, $noreg, 0, $noreg, killed [[COPY16]] :: (store 4 into %ir.fptr)
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; CHECK: RET 0
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bb.0.entry:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $edi, $rsi, $xmm0, $xmm1, $xmm2, $xmm3, $xmm4, $xmm5
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%10 = COPY $xmm5
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%9 = COPY $xmm4
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%8 = COPY $xmm3
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%7 = COPY $xmm2
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%6 = COPY $xmm1
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%5 = COPY $xmm0
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%4 = COPY $rsi
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%3 = COPY $edi
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%11 = COPY %3.sub_8bit
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TEST8ri killed %11, 1, implicit-def $eflags
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JE_1 %bb.2, implicit $eflags
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JMP_1 %bb.1
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bb.1.if:
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successors: %bb.3(0x80000000)
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%14 = VCMPSSZrr %7, %8, 0
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; check that cross domain copies are replaced with same domain copies.
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%15 = COPY %14
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%0 = COPY %15.sub_8bit
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JMP_1 %bb.3
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bb.2.else:
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successors: %bb.3(0x80000000)
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%12 = VCMPSSZrr %9, %10, 0
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; check that cross domain copies are replaced with same domain copies.
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%13 = COPY %12
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%1 = COPY %13.sub_8bit
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bb.3.exit:
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; check PHI, IMPLICIT_DEF, and INSERT_SUBREG replacers.
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%2 = PHI %1, %bb.2, %0, %bb.1
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%17 = IMPLICIT_DEF
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%16 = INSERT_SUBREG %17, %2, 1
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%18 = COPY %16
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%19 = COPY %6
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%21 = IMPLICIT_DEF
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%20 = VMOVSSZrrk %19, killed %18, killed %21, %5
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%22 = COPY %20
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VMOVSSZmr %4, 1, $noreg, 0, $noreg, killed %22 :: (store 4 into %ir.fptr)
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RET 0
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...
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---
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name: test_8bitops
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr64, preferred-register: '' }
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- { id: 1, class: vr512, preferred-register: '' }
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- { id: 2, class: vr512, preferred-register: '' }
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- { id: 3, class: vr512, preferred-register: '' }
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- { id: 4, class: vr512, preferred-register: '' }
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- { id: 5, class: vk8, preferred-register: '' }
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- { id: 6, class: gr32, preferred-register: '' }
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- { id: 7, class: gr8, preferred-register: '' }
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- { id: 8, class: gr32, preferred-register: '' }
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- { id: 9, class: gr32, preferred-register: '' }
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- { id: 10, class: vk8wm, preferred-register: '' }
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- { id: 11, class: vr512, preferred-register: '' }
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- { id: 12, class: gr8, preferred-register: '' }
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- { id: 13, class: gr8, preferred-register: '' }
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- { id: 14, class: gr8, preferred-register: '' }
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- { id: 15, class: gr8, preferred-register: '' }
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- { id: 16, class: gr8, preferred-register: '' }
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- { id: 17, class: gr8, preferred-register: '' }
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- { id: 18, class: gr8, preferred-register: '' }
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liveins:
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- { reg: '$rdi', virtual-reg: '%0' }
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- { reg: '$zmm0', virtual-reg: '%1' }
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- { reg: '$zmm1', virtual-reg: '%2' }
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- { reg: '$zmm2', virtual-reg: '%3' }
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- { reg: '$zmm3', virtual-reg: '%4' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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; CHECK-LABEL: name: test_8bitops
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $rdi, $zmm0, $zmm1, $zmm2, $zmm3
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; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
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; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
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; CHECK: [[COPY2:%[0-9]+]]:vr512 = COPY $zmm1
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; CHECK: [[COPY3:%[0-9]+]]:vr512 = COPY $zmm2
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; CHECK: [[COPY4:%[0-9]+]]:vr512 = COPY $zmm3
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; CHECK: [[VCMPPDZrri:%[0-9]+]]:vk8 = VCMPPDZrri [[COPY3]], [[COPY4]], 0
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; CHECK: [[COPY5:%[0-9]+]]:vk32 = COPY [[VCMPPDZrri]]
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; CHECK: [[COPY6:%[0-9]+]]:vk8 = COPY [[COPY5]]
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; CHECK: [[KSHIFTRBri:%[0-9]+]]:vk8 = KSHIFTRBri [[COPY6]], 2
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; CHECK: [[KSHIFTLBri:%[0-9]+]]:vk8 = KSHIFTLBri [[KSHIFTRBri]], 1
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; CHECK: [[KNOTBrr:%[0-9]+]]:vk8 = KNOTBrr [[KSHIFTLBri]]
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; CHECK: [[KORBrr:%[0-9]+]]:vk8 = KORBrr [[KNOTBrr]], [[KSHIFTRBri]]
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; CHECK: [[KANDBrr:%[0-9]+]]:vk8 = KANDBrr [[KORBrr]], [[KSHIFTLBri]]
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; CHECK: [[KXORBrr:%[0-9]+]]:vk8 = KXORBrr [[KANDBrr]], [[KSHIFTRBri]]
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; CHECK: [[KADDBrr:%[0-9]+]]:vk8 = KADDBrr [[KXORBrr]], [[KNOTBrr]]
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; CHECK: [[COPY7:%[0-9]+]]:vk32 = COPY [[KADDBrr]]
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; CHECK: [[COPY8:%[0-9]+]]:vk8wm = COPY [[COPY7]]
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; CHECK: [[VMOVAPDZrrk:%[0-9]+]]:vr512 = VMOVAPDZrrk [[COPY2]], killed [[COPY8]], [[COPY1]]
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; CHECK: VMOVAPDZmr [[COPY]], 1, $noreg, 0, $noreg, killed [[VMOVAPDZrrk]]
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: bb.2:
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; CHECK: RET 0
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bb.0:
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liveins: $rdi, $zmm0, $zmm1, $zmm2, $zmm3
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%0 = COPY $rdi
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%1 = COPY $zmm0
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%2 = COPY $zmm1
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%3 = COPY $zmm2
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%4 = COPY $zmm3
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%5 = VCMPPDZrri %3, %4, 0
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%6 = COPY %5
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%7 = COPY %6.sub_8bit
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%12 = SHR8ri %7, 2, implicit-def dead $eflags
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%13 = SHL8ri %12, 1, implicit-def dead $eflags
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%14 = NOT8r %13
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%15 = OR8rr %14, %12, implicit-def dead $eflags
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%16 = AND8rr %15, %13, implicit-def dead $eflags
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%17 = XOR8rr %16, %12, implicit-def dead $eflags
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%18 = ADD8rr %17, %14, implicit-def dead $eflags
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%8 = IMPLICIT_DEF
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%9 = INSERT_SUBREG %8, %18, 1
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%10 = COPY %9
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%11 = VMOVAPDZrrk %2, killed %10, %1
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VMOVAPDZmr %0, 1, $noreg, 0, $noreg, killed %11
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; FIXME We can't replace TEST with KTEST due to flag differences
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; TEST8rr %18, %18, implicit-def $eflags
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; JE_1 %bb.1, implicit $eflags
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; JMP_1 %bb.2
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bb.1:
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bb.2:
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RET 0
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...
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---
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name: test_16bitops
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr64, preferred-register: '' }
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- { id: 1, class: vr512, preferred-register: '' }
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- { id: 2, class: vr512, preferred-register: '' }
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- { id: 3, class: vr512, preferred-register: '' }
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- { id: 4, class: vr512, preferred-register: '' }
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- { id: 5, class: vk16, preferred-register: '' }
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- { id: 6, class: gr32, preferred-register: '' }
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- { id: 7, class: gr16, preferred-register: '' }
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- { id: 8, class: gr32, preferred-register: '' }
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- { id: 9, class: gr32, preferred-register: '' }
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- { id: 10, class: vk16wm, preferred-register: '' }
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- { id: 11, class: vr512, preferred-register: '' }
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- { id: 12, class: gr16, preferred-register: '' }
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- { id: 13, class: gr16, preferred-register: '' }
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- { id: 14, class: gr16, preferred-register: '' }
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- { id: 15, class: gr16, preferred-register: '' }
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- { id: 16, class: gr16, preferred-register: '' }
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- { id: 17, class: gr16, preferred-register: '' }
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liveins:
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- { reg: '$rdi', virtual-reg: '%0' }
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- { reg: '$zmm0', virtual-reg: '%1' }
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- { reg: '$zmm1', virtual-reg: '%2' }
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- { reg: '$zmm2', virtual-reg: '%3' }
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- { reg: '$zmm3', virtual-reg: '%4' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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; CHECK-LABEL: name: test_16bitops
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $rdi, $zmm0, $zmm1, $zmm2, $zmm3
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; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
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; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
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; CHECK: [[COPY2:%[0-9]+]]:vr512 = COPY $zmm1
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; CHECK: [[COPY3:%[0-9]+]]:vr512 = COPY $zmm2
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; CHECK: [[COPY4:%[0-9]+]]:vr512 = COPY $zmm3
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; CHECK: [[VCMPPSZrri:%[0-9]+]]:vk16 = VCMPPSZrri [[COPY3]], [[COPY4]], 0
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; CHECK: [[COPY5:%[0-9]+]]:vk32 = COPY [[VCMPPSZrri]]
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; CHECK: [[COPY6:%[0-9]+]]:vk16 = COPY [[COPY5]]
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; CHECK: [[KSHIFTRWri:%[0-9]+]]:vk16 = KSHIFTRWri [[COPY6]], 2
|
|
; CHECK: [[KSHIFTLWri:%[0-9]+]]:vk16 = KSHIFTLWri [[KSHIFTRWri]], 1
|
|
; CHECK: [[KNOTWrr:%[0-9]+]]:vk16 = KNOTWrr [[KSHIFTLWri]]
|
|
; CHECK: [[KORWrr:%[0-9]+]]:vk16 = KORWrr [[KNOTWrr]], [[KSHIFTRWri]]
|
|
; CHECK: [[KANDWrr:%[0-9]+]]:vk16 = KANDWrr [[KORWrr]], [[KSHIFTLWri]]
|
|
; CHECK: [[KXORWrr:%[0-9]+]]:vk16 = KXORWrr [[KANDWrr]], [[KSHIFTRWri]]
|
|
; CHECK: [[COPY7:%[0-9]+]]:vk32 = COPY [[KXORWrr]]
|
|
; CHECK: [[COPY8:%[0-9]+]]:vk16wm = COPY [[COPY7]]
|
|
; CHECK: [[VMOVAPSZrrk:%[0-9]+]]:vr512 = VMOVAPSZrrk [[COPY2]], killed [[COPY8]], [[COPY1]]
|
|
; CHECK: VMOVAPSZmr [[COPY]], 1, $noreg, 0, $noreg, killed [[VMOVAPSZrrk]]
|
|
; CHECK: bb.1:
|
|
; CHECK: successors: %bb.2(0x80000000)
|
|
; CHECK: bb.2:
|
|
; CHECK: RET 0
|
|
bb.0:
|
|
liveins: $rdi, $zmm0, $zmm1, $zmm2, $zmm3
|
|
|
|
%0 = COPY $rdi
|
|
%1 = COPY $zmm0
|
|
%2 = COPY $zmm1
|
|
%3 = COPY $zmm2
|
|
%4 = COPY $zmm3
|
|
|
|
%5 = VCMPPSZrri %3, %4, 0
|
|
%6 = COPY %5
|
|
%7 = COPY %6.sub_16bit
|
|
|
|
%12 = SHR16ri %7, 2, implicit-def dead $eflags
|
|
%13 = SHL16ri %12, 1, implicit-def dead $eflags
|
|
%14 = NOT16r %13
|
|
%15 = OR16rr %14, %12, implicit-def dead $eflags
|
|
%16 = AND16rr %15, %13, implicit-def dead $eflags
|
|
%17 = XOR16rr %16, %12, implicit-def dead $eflags
|
|
|
|
%8 = IMPLICIT_DEF
|
|
%9 = INSERT_SUBREG %8, %17, 3
|
|
%10 = COPY %9
|
|
%11 = VMOVAPSZrrk %2, killed %10, %1
|
|
VMOVAPSZmr %0, 1, $noreg, 0, $noreg, killed %11
|
|
|
|
; FIXME We can't replace TEST with KTEST due to flag differences
|
|
; FIXME TEST16rr %17, %17, implicit-def $eflags
|
|
; FIXME JE_1 %bb.1, implicit $eflags
|
|
; FIXME JMP_1 %bb.2
|
|
|
|
bb.1:
|
|
|
|
bb.2:
|
|
RET 0
|
|
|
|
...
|
|
---
|
|
name: test_32bitops
|
|
alignment: 4
|
|
exposesReturnsTwice: false
|
|
legalized: false
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gr64, preferred-register: '' }
|
|
- { id: 1, class: vr512, preferred-register: '' }
|
|
- { id: 2, class: vr512, preferred-register: '' }
|
|
- { id: 3, class: vk32wm, preferred-register: '' }
|
|
- { id: 4, class: vr512, preferred-register: '' }
|
|
- { id: 5, class: gr32, preferred-register: '' }
|
|
- { id: 6, class: gr32, preferred-register: '' }
|
|
- { id: 7, class: gr32, preferred-register: '' }
|
|
- { id: 8, class: gr32, preferred-register: '' }
|
|
- { id: 9, class: gr32, preferred-register: '' }
|
|
- { id: 10, class: gr32, preferred-register: '' }
|
|
- { id: 11, class: gr32, preferred-register: '' }
|
|
- { id: 12, class: gr32, preferred-register: '' }
|
|
- { id: 13, class: gr32, preferred-register: '' }
|
|
liveins:
|
|
- { reg: '$rdi', virtual-reg: '%0' }
|
|
- { reg: '$zmm0', virtual-reg: '%1' }
|
|
- { reg: '$zmm1', virtual-reg: '%2' }
|
|
frameInfo:
|
|
isFrameAddressTaken: false
|
|
isReturnAddressTaken: false
|
|
hasStackMap: false
|
|
hasPatchPoint: false
|
|
stackSize: 0
|
|
offsetAdjustment: 0
|
|
maxAlignment: 0
|
|
adjustsStack: false
|
|
hasCalls: false
|
|
stackProtector: ''
|
|
maxCallFrameSize: 4294967295
|
|
hasOpaqueSPAdjustment: false
|
|
hasVAStart: false
|
|
hasMustTailInVarArgFunc: false
|
|
savePoint: ''
|
|
restorePoint: ''
|
|
fixedStack:
|
|
stack:
|
|
constants:
|
|
body: |
|
|
; CHECK-LABEL: name: test_32bitops
|
|
; CHECK: bb.0:
|
|
; CHECK: successors: %bb.1(0x80000000)
|
|
; CHECK: liveins: $rdi, $zmm0, $zmm1
|
|
; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
|
|
; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
|
|
; CHECK: [[COPY2:%[0-9]+]]:vr512 = COPY $zmm1
|
|
; CHECK: [[KMOVDkm:%[0-9]+]]:vk32 = KMOVDkm [[COPY]], 1, $noreg, 0, $noreg
|
|
; CHECK: [[KSHIFTRDri:%[0-9]+]]:vk32 = KSHIFTRDri [[KMOVDkm]], 2
|
|
; CHECK: [[KSHIFTLDri:%[0-9]+]]:vk32 = KSHIFTLDri [[KSHIFTRDri]], 1
|
|
; CHECK: [[KNOTDrr:%[0-9]+]]:vk32 = KNOTDrr [[KSHIFTLDri]]
|
|
; CHECK: [[KORDrr:%[0-9]+]]:vk32 = KORDrr [[KNOTDrr]], [[KSHIFTRDri]]
|
|
; CHECK: [[KANDDrr:%[0-9]+]]:vk32 = KANDDrr [[KORDrr]], [[KSHIFTLDri]]
|
|
; CHECK: [[KXORDrr:%[0-9]+]]:vk32 = KXORDrr [[KANDDrr]], [[KSHIFTRDri]]
|
|
; CHECK: [[KANDNDrr:%[0-9]+]]:vk32 = KANDNDrr [[KXORDrr]], [[KORDrr]]
|
|
; CHECK: [[KADDDrr:%[0-9]+]]:vk32 = KADDDrr [[KANDNDrr]], [[KXORDrr]]
|
|
; CHECK: [[COPY3:%[0-9]+]]:vk32wm = COPY [[KADDDrr]]
|
|
; CHECK: [[VMOVDQU16Zrrk:%[0-9]+]]:vr512 = VMOVDQU16Zrrk [[COPY2]], killed [[COPY3]], [[COPY1]]
|
|
; CHECK: VMOVDQA32Zmr [[COPY]], 1, $noreg, 0, $noreg, killed [[VMOVDQU16Zrrk]]
|
|
; CHECK: bb.1:
|
|
; CHECK: successors: %bb.2(0x80000000)
|
|
; CHECK: bb.2:
|
|
; CHECK: RET 0
|
|
bb.0:
|
|
liveins: $rdi, $zmm0, $zmm1
|
|
|
|
%0 = COPY $rdi
|
|
%1 = COPY $zmm0
|
|
%2 = COPY $zmm1
|
|
|
|
%5 = MOV32rm %0, 1, $noreg, 0, $noreg
|
|
%6 = SHR32ri %5, 2, implicit-def dead $eflags
|
|
%7 = SHL32ri %6, 1, implicit-def dead $eflags
|
|
%8 = NOT32r %7
|
|
%9 = OR32rr %8, %6, implicit-def dead $eflags
|
|
%10 = AND32rr %9, %7, implicit-def dead $eflags
|
|
%11 = XOR32rr %10, %6, implicit-def dead $eflags
|
|
%12 = ANDN32rr %11, %9, implicit-def dead $eflags
|
|
%13 = ADD32rr %12, %11, implicit-def dead $eflags
|
|
|
|
%3 = COPY %13
|
|
%4 = VMOVDQU16Zrrk %2, killed %3, %1
|
|
VMOVDQA32Zmr %0, 1, $noreg, 0, $noreg, killed %4
|
|
|
|
; FIXME We can't replace TEST with KTEST due to flag differences
|
|
; FIXME TEST32rr %13, %13, implicit-def $eflags
|
|
; FIXME JE_1 %bb.1, implicit $eflags
|
|
; FIXME JMP_1 %bb.2
|
|
|
|
bb.1:
|
|
|
|
bb.2:
|
|
RET 0
|
|
|
|
...
|
|
---
|
|
name: test_64bitops
|
|
alignment: 4
|
|
exposesReturnsTwice: false
|
|
legalized: false
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gr64, preferred-register: '' }
|
|
- { id: 1, class: vr512, preferred-register: '' }
|
|
- { id: 2, class: vr512, preferred-register: '' }
|
|
- { id: 3, class: vk64wm, preferred-register: '' }
|
|
- { id: 4, class: vr512, preferred-register: '' }
|
|
- { id: 5, class: gr64, preferred-register: '' }
|
|
- { id: 6, class: gr64, preferred-register: '' }
|
|
- { id: 7, class: gr64, preferred-register: '' }
|
|
- { id: 8, class: gr64, preferred-register: '' }
|
|
- { id: 9, class: gr64, preferred-register: '' }
|
|
- { id: 10, class: gr64, preferred-register: '' }
|
|
- { id: 11, class: gr64, preferred-register: '' }
|
|
- { id: 12, class: gr64, preferred-register: '' }
|
|
- { id: 13, class: gr64, preferred-register: '' }
|
|
liveins:
|
|
- { reg: '$rdi', virtual-reg: '%0' }
|
|
- { reg: '$zmm0', virtual-reg: '%1' }
|
|
- { reg: '$zmm1', virtual-reg: '%2' }
|
|
frameInfo:
|
|
isFrameAddressTaken: false
|
|
isReturnAddressTaken: false
|
|
hasStackMap: false
|
|
hasPatchPoint: false
|
|
stackSize: 0
|
|
offsetAdjustment: 0
|
|
maxAlignment: 0
|
|
adjustsStack: false
|
|
hasCalls: false
|
|
stackProtector: ''
|
|
maxCallFrameSize: 4294967295
|
|
hasOpaqueSPAdjustment: false
|
|
hasVAStart: false
|
|
hasMustTailInVarArgFunc: false
|
|
savePoint: ''
|
|
restorePoint: ''
|
|
fixedStack:
|
|
stack:
|
|
constants:
|
|
body: |
|
|
; CHECK-LABEL: name: test_64bitops
|
|
; CHECK: bb.0:
|
|
; CHECK: successors: %bb.1(0x80000000)
|
|
; CHECK: liveins: $rdi, $zmm0, $zmm1
|
|
; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
|
|
; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
|
|
; CHECK: [[COPY2:%[0-9]+]]:vr512 = COPY $zmm1
|
|
; CHECK: [[KMOVQkm:%[0-9]+]]:vk64 = KMOVQkm [[COPY]], 1, $noreg, 0, $noreg
|
|
; CHECK: [[KSHIFTRQri:%[0-9]+]]:vk64 = KSHIFTRQri [[KMOVQkm]], 2
|
|
; CHECK: [[KSHIFTLQri:%[0-9]+]]:vk64 = KSHIFTLQri [[KSHIFTRQri]], 1
|
|
; CHECK: [[KNOTQrr:%[0-9]+]]:vk64 = KNOTQrr [[KSHIFTLQri]]
|
|
; CHECK: [[KORQrr:%[0-9]+]]:vk64 = KORQrr [[KNOTQrr]], [[KSHIFTRQri]]
|
|
; CHECK: [[KANDQrr:%[0-9]+]]:vk64 = KANDQrr [[KORQrr]], [[KSHIFTLQri]]
|
|
; CHECK: [[KXORQrr:%[0-9]+]]:vk64 = KXORQrr [[KANDQrr]], [[KSHIFTRQri]]
|
|
; CHECK: [[KANDNQrr:%[0-9]+]]:vk64 = KANDNQrr [[KXORQrr]], [[KORQrr]]
|
|
; CHECK: [[KADDQrr:%[0-9]+]]:vk64 = KADDQrr [[KANDNQrr]], [[KXORQrr]]
|
|
; CHECK: [[COPY3:%[0-9]+]]:vk64wm = COPY [[KADDQrr]]
|
|
; CHECK: [[VMOVDQU8Zrrk:%[0-9]+]]:vr512 = VMOVDQU8Zrrk [[COPY2]], killed [[COPY3]], [[COPY1]]
|
|
; CHECK: VMOVDQA32Zmr [[COPY]], 1, $noreg, 0, $noreg, killed [[VMOVDQU8Zrrk]]
|
|
; CHECK: bb.1:
|
|
; CHECK: successors: %bb.2(0x80000000)
|
|
; CHECK: bb.2:
|
|
; CHECK: RET 0
|
|
bb.0:
|
|
liveins: $rdi, $zmm0, $zmm1
|
|
|
|
%0 = COPY $rdi
|
|
%1 = COPY $zmm0
|
|
%2 = COPY $zmm1
|
|
|
|
%5 = MOV64rm %0, 1, $noreg, 0, $noreg
|
|
%6 = SHR64ri %5, 2, implicit-def dead $eflags
|
|
%7 = SHL64ri %6, 1, implicit-def dead $eflags
|
|
%8 = NOT64r %7
|
|
%9 = OR64rr %8, %6, implicit-def dead $eflags
|
|
%10 = AND64rr %9, %7, implicit-def dead $eflags
|
|
%11 = XOR64rr %10, %6, implicit-def dead $eflags
|
|
%12 = ANDN64rr %11, %9, implicit-def dead $eflags
|
|
%13 = ADD64rr %12, %11, implicit-def dead $eflags
|
|
|
|
%3 = COPY %13
|
|
%4 = VMOVDQU8Zrrk %2, killed %3, %1
|
|
VMOVDQA32Zmr %0, 1, $noreg, 0, $noreg, killed %4
|
|
|
|
; FIXME We can't replace TEST with KTEST due to flag differences
|
|
; FIXME TEST64rr %13, %13, implicit-def $eflags
|
|
; FIXME JE_1 %bb.1, implicit $eflags
|
|
; FIXME JMP_1 %bb.2
|
|
|
|
bb.1:
|
|
|
|
bb.2:
|
|
RET 0
|
|
|
|
...
|
|
---
|
|
name: test_16bitext
|
|
alignment: 4
|
|
exposesReturnsTwice: false
|
|
legalized: false
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gr64, preferred-register: '' }
|
|
- { id: 1, class: vr512, preferred-register: '' }
|
|
- { id: 2, class: vr512, preferred-register: '' }
|
|
- { id: 3, class: vk16wm, preferred-register: '' }
|
|
- { id: 4, class: vr512, preferred-register: '' }
|
|
- { id: 5, class: gr16, preferred-register: '' }
|
|
- { id: 6, class: gr16, preferred-register: '' }
|
|
liveins:
|
|
- { reg: '$rdi', virtual-reg: '%0' }
|
|
- { reg: '$zmm0', virtual-reg: '%1' }
|
|
- { reg: '$zmm1', virtual-reg: '%2' }
|
|
frameInfo:
|
|
isFrameAddressTaken: false
|
|
isReturnAddressTaken: false
|
|
hasStackMap: false
|
|
hasPatchPoint: false
|
|
stackSize: 0
|
|
offsetAdjustment: 0
|
|
maxAlignment: 0
|
|
adjustsStack: false
|
|
hasCalls: false
|
|
stackProtector: ''
|
|
maxCallFrameSize: 4294967295
|
|
hasOpaqueSPAdjustment: false
|
|
hasVAStart: false
|
|
hasMustTailInVarArgFunc: false
|
|
savePoint: ''
|
|
restorePoint: ''
|
|
fixedStack:
|
|
stack:
|
|
constants:
|
|
body: |
|
|
bb.0:
|
|
liveins: $rdi, $zmm0, $zmm1
|
|
|
|
; CHECK-LABEL: name: test_16bitext
|
|
; CHECK: liveins: $rdi, $zmm0, $zmm1
|
|
; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
|
|
; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
|
|
; CHECK: [[COPY2:%[0-9]+]]:vr512 = COPY $zmm1
|
|
; CHECK: [[KMOVBkm:%[0-9]+]]:vk8 = KMOVBkm [[COPY]], 1, $noreg, 0, $noreg
|
|
; CHECK: [[COPY3:%[0-9]+]]:vk16 = COPY [[KMOVBkm]]
|
|
; CHECK: [[KNOTWrr:%[0-9]+]]:vk16 = KNOTWrr [[COPY3]]
|
|
; CHECK: [[COPY4:%[0-9]+]]:vk16wm = COPY [[KNOTWrr]]
|
|
; CHECK: [[VMOVAPSZrrk:%[0-9]+]]:vr512 = VMOVAPSZrrk [[COPY2]], killed [[COPY4]], [[COPY1]]
|
|
; CHECK: VMOVAPSZmr [[COPY]], 1, $noreg, 0, $noreg, killed [[VMOVAPSZrrk]]
|
|
; CHECK: RET 0
|
|
%0 = COPY $rdi
|
|
%1 = COPY $zmm0
|
|
%2 = COPY $zmm1
|
|
|
|
%5 = MOVZX16rm8 %0, 1, $noreg, 0, $noreg
|
|
%6 = NOT16r %5
|
|
|
|
%3 = COPY %6
|
|
%4 = VMOVAPSZrrk %2, killed %3, %1
|
|
VMOVAPSZmr %0, 1, $noreg, 0, $noreg, killed %4
|
|
RET 0
|
|
|
|
...
|
|
---
|
|
name: test_32bitext
|
|
alignment: 4
|
|
exposesReturnsTwice: false
|
|
legalized: false
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gr64, preferred-register: '' }
|
|
- { id: 1, class: vr512, preferred-register: '' }
|
|
- { id: 2, class: vr512, preferred-register: '' }
|
|
- { id: 3, class: vk64wm, preferred-register: '' }
|
|
- { id: 4, class: vr512, preferred-register: '' }
|
|
- { id: 5, class: gr32, preferred-register: '' }
|
|
- { id: 6, class: gr32, preferred-register: '' }
|
|
- { id: 7, class: gr32, preferred-register: '' }
|
|
liveins:
|
|
- { reg: '$rdi', virtual-reg: '%0' }
|
|
- { reg: '$zmm0', virtual-reg: '%1' }
|
|
- { reg: '$zmm1', virtual-reg: '%2' }
|
|
frameInfo:
|
|
isFrameAddressTaken: false
|
|
isReturnAddressTaken: false
|
|
hasStackMap: false
|
|
hasPatchPoint: false
|
|
stackSize: 0
|
|
offsetAdjustment: 0
|
|
maxAlignment: 0
|
|
adjustsStack: false
|
|
hasCalls: false
|
|
stackProtector: ''
|
|
maxCallFrameSize: 4294967295
|
|
hasOpaqueSPAdjustment: false
|
|
hasVAStart: false
|
|
hasMustTailInVarArgFunc: false
|
|
savePoint: ''
|
|
restorePoint: ''
|
|
fixedStack:
|
|
stack:
|
|
constants:
|
|
body: |
|
|
bb.0:
|
|
liveins: $rdi, $zmm0, $zmm1
|
|
|
|
; CHECK-LABEL: name: test_32bitext
|
|
; CHECK: liveins: $rdi, $zmm0, $zmm1
|
|
; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
|
|
; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
|
|
; CHECK: [[COPY2:%[0-9]+]]:vr512 = COPY $zmm1
|
|
; CHECK: [[KMOVBkm:%[0-9]+]]:vk8 = KMOVBkm [[COPY]], 1, $noreg, 0, $noreg
|
|
; CHECK: [[COPY3:%[0-9]+]]:vk32 = COPY [[KMOVBkm]]
|
|
; CHECK: [[KMOVWkm:%[0-9]+]]:vk16 = KMOVWkm [[COPY]], 1, $noreg, 0, $noreg
|
|
; CHECK: [[COPY4:%[0-9]+]]:vk32 = COPY [[KMOVWkm]]
|
|
; CHECK: [[KADDDrr:%[0-9]+]]:vk32 = KADDDrr [[COPY3]], [[COPY4]]
|
|
; CHECK: [[COPY5:%[0-9]+]]:vk64wm = COPY [[KADDDrr]]
|
|
; CHECK: [[VMOVDQU16Zrrk:%[0-9]+]]:vr512 = VMOVDQU16Zrrk [[COPY2]], killed [[COPY5]], [[COPY1]]
|
|
; CHECK: VMOVDQA32Zmr [[COPY]], 1, $noreg, 0, $noreg, killed [[VMOVDQU16Zrrk]]
|
|
; CHECK: RET 0
|
|
%0 = COPY $rdi
|
|
%1 = COPY $zmm0
|
|
%2 = COPY $zmm1
|
|
|
|
%5 = MOVZX32rm8 %0, 1, $noreg, 0, $noreg
|
|
%6 = MOVZX32rm16 %0, 1, $noreg, 0, $noreg
|
|
%7 = ADD32rr %5, %6, implicit-def dead $eflags
|
|
|
|
%3 = COPY %7
|
|
%4 = VMOVDQU16Zrrk %2, killed %3, %1
|
|
VMOVDQA32Zmr %0, 1, $noreg, 0, $noreg, killed %4
|
|
RET 0
|
|
|
|
...
|
|
---
|
|
name: test_64bitext
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr64, preferred-register: '' }
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- { id: 1, class: vr512, preferred-register: '' }
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- { id: 2, class: vr512, preferred-register: '' }
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- { id: 3, class: vk64wm, preferred-register: '' }
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- { id: 4, class: vr512, preferred-register: '' }
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- { id: 5, class: gr64, preferred-register: '' }
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- { id: 6, class: gr64, preferred-register: '' }
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- { id: 7, class: gr64, preferred-register: '' }
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liveins:
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- { reg: '$rdi', virtual-reg: '%0' }
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- { reg: '$zmm0', virtual-reg: '%1' }
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- { reg: '$zmm1', virtual-reg: '%2' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0:
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liveins: $rdi, $zmm0, $zmm1
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; CHECK-LABEL: name: test_64bitext
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; CHECK: liveins: $rdi, $zmm0, $zmm1
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; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
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; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm0
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; CHECK: [[COPY2:%[0-9]+]]:vr512 = COPY $zmm1
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; CHECK: [[KMOVBkm:%[0-9]+]]:vk8 = KMOVBkm [[COPY]], 1, $noreg, 0, $noreg
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; CHECK: [[COPY3:%[0-9]+]]:vk64 = COPY [[KMOVBkm]]
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; CHECK: [[KMOVWkm:%[0-9]+]]:vk16 = KMOVWkm [[COPY]], 1, $noreg, 0, $noreg
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; CHECK: [[COPY4:%[0-9]+]]:vk64 = COPY [[KMOVWkm]]
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; CHECK: [[KADDQrr:%[0-9]+]]:vk64 = KADDQrr [[COPY3]], [[COPY4]]
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; CHECK: [[COPY5:%[0-9]+]]:vk64wm = COPY [[KADDQrr]]
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; CHECK: [[VMOVDQU8Zrrk:%[0-9]+]]:vr512 = VMOVDQU8Zrrk [[COPY2]], killed [[COPY5]], [[COPY1]]
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; CHECK: VMOVDQA32Zmr [[COPY]], 1, $noreg, 0, $noreg, killed [[VMOVDQU8Zrrk]]
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; CHECK: RET 0
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%0 = COPY $rdi
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%1 = COPY $zmm0
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%2 = COPY $zmm1
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%5 = MOVZX64rm8 %0, 1, $noreg, 0, $noreg
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%6 = MOVZX64rm16 %0, 1, $noreg, 0, $noreg
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%7 = ADD64rr %5, %6, implicit-def dead $eflags
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%3 = COPY %7
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%4 = VMOVDQU8Zrrk %2, killed %3, %1
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VMOVDQA32Zmr %0, 1, $noreg, 0, $noreg, killed %4
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RET 0
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...
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