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llvm-mirror/test/Transforms/LoopVectorize
David Green 5da8fa266d [ARM] Teach the Arm cost model that a Shift can be folded into other instructions
This attempts to teach the cost model in Arm that code such as:
  %s = shl i32 %a, 3
  %a = and i32 %s, %b
Can under Arm or Thumb2 become:
  and r0, r1, r2, lsl #3

So the cost of the shift can essentially be free. To do this without
trying to artificially adjust the cost of the "and" instruction, it
needs to get the users of the shl and check if they are a type of
instruction that the shift can be folded into. And so it needs to have
access to the actual instruction in getArithmeticInstrCost, which if
available is added as an extra parameter much like getCastInstrCost.

We otherwise limit it to shifts with a single user, which should
hopefully handle most of the cases. The list of instruction that the
shift can be folded into include ADC, ADD, AND, BIC, CMP, EOR, MVN, ORR,
ORN, RSB, SBC and SUB. This translates to Add, Sub, And, Or, Xor and
ICmp.

Differential Revision: https://reviews.llvm.org/D70966
2019-12-09 10:24:33 +00:00
..
AArch64
AMDGPU
ARM [ARM] Teach the Arm cost model that a Shift can be folded into other instructions 2019-12-09 10:24:33 +00:00
Hexagon
PowerPC recommit: [LoopVectorize][PowerPC] Estimate int and float register pressure separately in loop-vectorize 2019-10-12 02:53:04 +00:00
SystemZ [LV] Pick correct BB as insert point when fixing PHI for FORs. 2019-12-07 19:32:00 +00:00
X86 [LV] Scalar with predication must not be uniform 2019-12-03 19:50:24 +02:00
XCore
12-12-11-if-conv.ll
2012-10-20-infloop.ll
2012-10-22-isconsec.ll
2016-07-27-loop-vec.ll
align.ll
bsd_regex.ll
bzip_reverse_loops.ll
calloc.ll
cast-induction.ll
conditional-assignment.ll
consec_no_gep.ll
consecutive-ptr-uniforms.ll
control-flow.ll
cpp-new-array.ll
dbg.value.ll
dead_instructions.ll
debugloc.ll
demanded-bits-of-pointer-instruction.ll
diag-missing-instr-debug-loc.ll
diag-with-hotness-info-2.ll
diag-with-hotness-info.ll
disable_nonforced_enable.ll
disable_nonforced.ll
discriminator.ll
ee-crash.ll
exact.ll
explicit_outer_detection.ll
explicit_outer_nonuniform_inner.ll
explicit_outer_uniform_diverg_branch.ll
fcmp-vectorize.ll
first-order-recurrence-complex.ll [IVDescriptors] Skip FOR where we have multiple sink points for now. 2019-11-28 22:18:47 +01:00
first-order-recurrence-multiply-recurrences.ll Recommit f0c2a5a "[LV] Generalize conditions for sinking instrs for first order recurrences." 2019-11-24 21:21:55 +00:00
first-order-recurrence.ll [LV] Apply sink-after & interleave-groups as VPlan transformations (NFCI) 2019-11-09 20:52:25 +02:00
fix-reduction-dbg.ll
flags.ll
float-induction.ll
float-minmax-instruction-flag.ll
float-reduction.ll
fneg.ll
followup.ll
funcall.ll
gcc-examples.ll
gep_with_bitcast.ll
global_alias.ll
hints-trans.ll
hoist-loads.ll [LoopVectorize] Leverage speculation safety to avoid masked.loads 2019-09-09 20:54:13 +00:00
i8-induction.ll
icmp-uniforms.ll
if-conv-crash.ll
if-conversion-edgemasks.ll
if-conversion-nest.ll [InstCombine] Revert rL341831: relax one-use check in foldICmpAddConstant() (PR44100) 2019-12-02 18:06:15 +03:00
if-conversion-reduction.ll
if-conversion.ll
if-pred-non-void.ll
if-pred-not-when-safe.ll
if-pred-stores.ll
if-reduction.ll
incorrect-dom-info.ll
increment.ll
induction_plus.ll
induction-step.ll
induction.ll
infiniteloop.ll
int_sideeffect.ll
interleaved-accesses-1.ll
interleaved-accesses-2.ll
interleaved-accesses-3.ll
interleaved-accesses-alias.ll
interleaved-accesses-masked-group.ll
interleaved-accesses-pred-stores.ll
interleaved-accesses-uniform-load.ll [LV] Apply sink-after & interleave-groups as VPlan transformations (NFCI) 2019-11-09 20:52:25 +02:00
interleaved-accesses.ll
interleaved-acess-with-remarks.ll
intrinsic.ll
invariant-store-vectorization.ll
iv_outside_user.ll
lcssa-crash.ll
libcall-remark.ll
lifetime.ll
loop-form.ll
loop-legality-checks.ll
loop-scalars.ll
loop-vect-memdep.ll
loop-vect-option.ll
memdep.ll
metadata-unroll.ll
metadata-width.ll
metadata.ll
middle-block-dbg.ll
miniters.ll
minmax_reduction.ll
multi-use-reduction-bug.ll
multiple-address-spaces.ll
multiple-strides-vectorization.ll
no_array_bounds.ll
no_idiv_reduction.ll
no_int_induction.ll
no_outside_user.ll
no_switch_disable_vectorization.ll
no_switch.ll
no-interleave-up-front.ll
noalias-md-licm.ll
noalias-md.ll
nofloat-report.ll [LV][NFC] Share the LV illegality reporting with LoopVectorize. 2019-08-06 06:08:48 +00:00
nofloat.ll
non-const-n.ll
nontemporal.ll
nsw-crash.ll
opt.ll
optsize.ll [LV] Emitting SCEV checks with OptForSize 2019-10-09 13:19:41 +00:00
outer_loop_test1.ll
outer_loop_test2.ll
partial-lcssa.ll
phi-cost.ll
phi-hang.ll
pr25281.ll
pr28541.ll
pr30654-phiscev-sext-trunc.ll
pr30806-phi-scev.ll
pr30806.ll
pr31098.ll
pr31190.ll
pr32859.ll
pr33706.ll
pr34681.ll
pr35743.ll
pr35773.ll
pr36311.ll
pr36983.ll
pr37248.ll
pr37515.ll
pr38697.ll
pr38800.ll
pr39099.ll
pr39417-optsize-scevchecks.ll
pr43166-fold-tail-by-masking.ll [LV] Fix miscompiles by adding non-header PHI nodes to AllowedExit 2019-09-03 09:33:55 +00:00
preserve-dbg-loc-and-loop-metadata.ll
ptr_loops.ll
ptr-induction.ll
read-only.ll
reduction-small-size.ll
reduction.ll
remove_metadata.ll
reverse_induction.ll
reverse_iter.ll
runtime-check-address-space.ll
runtime-check-readonly-address-space.ll
runtime-check-readonly.ll
runtime-check.ll [InstCombine] Revert rL341831: relax one-use check in foldICmpAddConstant() (PR44100) 2019-12-02 18:06:15 +03:00
runtime-limit.ll
safegep.ll
same-base-access.ll
scalar_after_vectorization.ll
scalar-select.ll
scev-exitlim-crash.ll
simple-unroll.ll
skip-iterations.ll
small-loop.ll
start-non-zero.ll
store-shuffle-bug.ll
struct_access.ll
tbaa-nodep.ll
tripcount.ll
undef-inst-bug.ll
unroll_novec.ll
unroll-novec-memcheck-metadata.ll
unroll.ll
unsafe-dep-remark.ll
unsized-pointee-crash.ll
value-ptr-bug.ll
vect-phiscev-sext-trunc.ll
vect.omp.persistence.ll
vect.stats.ll
vector-geps.ll
vector-intrinsic-call-cost.ll
vectorize-once.ll
version-mem-access.ll
vplan_hcfg_stress_test.ll
vplan-stress-test-no-explict-vf.ll
write-only.ll
zero-sized-pointee-crash.ll