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5e00f501ff
The basic issue here is that bottom-up isel is matching the branch and compare, and was failing to fold the load into the branch/compare combo. Fixing this (by allowing folding into any instruction of a sequence that is selected) allows us to produce things like: cmpb $0, 52(%rax) je LBB4_2 instead of: movb 52(%rax), %cl cmpb $0, %cl je LBB4_2 This makes the generated -O0 code run a bit faster, but also speeds up compile time by putting less pressure on the register allocator and generating less code. This was one of the biggest classes of missing load folding. Implementing this shrinks 176.gcc's c-decl.s (as a random example) by about 4% in (verbose-asm) line count. llvm-svn: 129656
36 lines
1.0 KiB
LLVM
36 lines
1.0 KiB
LLVM
; RUN: llc < %s -fast-isel -O0 -regalloc=fast | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-apple-darwin10.0.0"
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; Make sure that fast-isel folds the immediate into the binop even though it
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; is non-canonical.
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define i32 @test1(i32 %i) nounwind ssp {
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%and = and i32 8, %i
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ret i32 %and
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}
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; CHECK: test1:
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; CHECK: andl $8,
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; rdar://9289512 - The load should fold into the compare.
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define void @test2(i64 %x) nounwind ssp {
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entry:
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%x.addr = alloca i64, align 8
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store i64 %x, i64* %x.addr, align 8
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%tmp = load i64* %x.addr, align 8
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%cmp = icmp sgt i64 %tmp, 42
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret void
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}
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; CHECK: test2:
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; CHECK: movq %rdi, -8(%rsp)
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; CHECK: cmpq $42, -8(%rsp)
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