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b9ec29d7c5
This commit adds a weak variant of the cmpxchg operation, as described in C++11. A cmpxchg instruction with this modifier is permitted to fail to store, even if the comparison indicated it should. As a result, cmpxchg instructions must return a flag indicating success in addition to their original iN value loaded. Thus, for uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The second flag is 1 when the store succeeded. At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been added as the natural representation for the new cmpxchg instructions. It is a strong cmpxchg. By default this gets Expanded to the existing ATOMIC_CMP_SWAP during Legalization, so existing backends should see no change in behaviour. If they wish to deal with the enhanced node instead, they can call setOperationAction on it. Beware: as a node with 2 results, it cannot be selected from TableGen. Currently, no use is made of the extra information provided in this patch. Test updates are almost entirely adapting the input IR to the new scheme. Summary for out of tree users: ------------------------------ + Legacy Bitcode files are upgraded during read. + Legacy assembly IR files will be invalid. + Front-ends must adapt to different type for "cmpxchg". + Backends should be unaffected by default. llvm-svn: 210903
149 lines
4.4 KiB
C++
149 lines
4.4 KiB
C++
//===- LowerAtomic.cpp - Lower atomic intrinsics --------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass lowers atomic intrinsics to non-atomic form for use in a known
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// non-preemptible environment.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/Pass.h"
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using namespace llvm;
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#define DEBUG_TYPE "loweratomic"
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static bool LowerAtomicCmpXchgInst(AtomicCmpXchgInst *CXI) {
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IRBuilder<> Builder(CXI->getParent(), CXI);
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Value *Ptr = CXI->getPointerOperand();
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Value *Cmp = CXI->getCompareOperand();
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Value *Val = CXI->getNewValOperand();
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LoadInst *Orig = Builder.CreateLoad(Ptr);
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Value *Equal = Builder.CreateICmpEQ(Orig, Cmp);
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Value *Res = Builder.CreateSelect(Equal, Val, Orig);
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Builder.CreateStore(Res, Ptr);
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Res = Builder.CreateInsertValue(UndefValue::get(CXI->getType()), Orig, 0);
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Res = Builder.CreateInsertValue(Res, Equal, 1);
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CXI->replaceAllUsesWith(Res);
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CXI->eraseFromParent();
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return true;
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}
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static bool LowerAtomicRMWInst(AtomicRMWInst *RMWI) {
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IRBuilder<> Builder(RMWI->getParent(), RMWI);
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Value *Ptr = RMWI->getPointerOperand();
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Value *Val = RMWI->getValOperand();
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LoadInst *Orig = Builder.CreateLoad(Ptr);
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Value *Res = nullptr;
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switch (RMWI->getOperation()) {
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default: llvm_unreachable("Unexpected RMW operation");
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case AtomicRMWInst::Xchg:
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Res = Val;
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break;
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case AtomicRMWInst::Add:
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Res = Builder.CreateAdd(Orig, Val);
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break;
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case AtomicRMWInst::Sub:
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Res = Builder.CreateSub(Orig, Val);
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break;
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case AtomicRMWInst::And:
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Res = Builder.CreateAnd(Orig, Val);
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break;
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case AtomicRMWInst::Nand:
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Res = Builder.CreateNot(Builder.CreateAnd(Orig, Val));
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break;
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case AtomicRMWInst::Or:
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Res = Builder.CreateOr(Orig, Val);
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break;
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case AtomicRMWInst::Xor:
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Res = Builder.CreateXor(Orig, Val);
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break;
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case AtomicRMWInst::Max:
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Res = Builder.CreateSelect(Builder.CreateICmpSLT(Orig, Val),
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Val, Orig);
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break;
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case AtomicRMWInst::Min:
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Res = Builder.CreateSelect(Builder.CreateICmpSLT(Orig, Val),
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Orig, Val);
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break;
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case AtomicRMWInst::UMax:
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Res = Builder.CreateSelect(Builder.CreateICmpULT(Orig, Val),
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Val, Orig);
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break;
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case AtomicRMWInst::UMin:
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Res = Builder.CreateSelect(Builder.CreateICmpULT(Orig, Val),
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Orig, Val);
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break;
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}
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Builder.CreateStore(Res, Ptr);
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RMWI->replaceAllUsesWith(Orig);
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RMWI->eraseFromParent();
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return true;
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}
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static bool LowerFenceInst(FenceInst *FI) {
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FI->eraseFromParent();
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return true;
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}
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static bool LowerLoadInst(LoadInst *LI) {
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LI->setAtomic(NotAtomic);
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return true;
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}
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static bool LowerStoreInst(StoreInst *SI) {
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SI->setAtomic(NotAtomic);
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return true;
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}
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namespace {
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struct LowerAtomic : public BasicBlockPass {
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static char ID;
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LowerAtomic() : BasicBlockPass(ID) {
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initializeLowerAtomicPass(*PassRegistry::getPassRegistry());
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}
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bool runOnBasicBlock(BasicBlock &BB) override {
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if (skipOptnoneFunction(BB))
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return false;
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bool Changed = false;
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for (BasicBlock::iterator DI = BB.begin(), DE = BB.end(); DI != DE; ) {
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Instruction *Inst = DI++;
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if (FenceInst *FI = dyn_cast<FenceInst>(Inst))
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Changed |= LowerFenceInst(FI);
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else if (AtomicCmpXchgInst *CXI = dyn_cast<AtomicCmpXchgInst>(Inst))
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Changed |= LowerAtomicCmpXchgInst(CXI);
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else if (AtomicRMWInst *RMWI = dyn_cast<AtomicRMWInst>(Inst))
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Changed |= LowerAtomicRMWInst(RMWI);
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else if (LoadInst *LI = dyn_cast<LoadInst>(Inst)) {
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if (LI->isAtomic())
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LowerLoadInst(LI);
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} else if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
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if (SI->isAtomic())
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LowerStoreInst(SI);
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}
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}
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return Changed;
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}
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};
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}
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char LowerAtomic::ID = 0;
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INITIALIZE_PASS(LowerAtomic, "loweratomic",
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"Lower atomic intrinsics to non-atomic form",
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false, false)
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Pass *llvm::createLowerAtomicPass() { return new LowerAtomic(); }
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