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5ed377ecc1
Summary: In AArch64InstrInfo::foldMemoryOperandImpl, catch more cases where the COPY being spilled is copying from WZR/XZR, but the source register is not in the COPY destination register's regclass. For example, when spilling: %vreg0 = COPY %XZR ; %vreg0:GPR64common without this change, the code in TargetInstrInfo::foldMemoryOperand() and canFoldCopy() that normally handles cases like this would fail to optimize since %XZR is not in GPR64common. So the spill code generated would be: %vreg0 = COPY %XZR STR %vreg instead of the new code generated: STR %XZR Reviewers: qcolombet, MatzeB Subscribers: mcrosier, aemerson, t.p.northover, llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D26976 llvm-svn: 288176
85 lines
2.4 KiB
LLVM
85 lines
2.4 KiB
LLVM
; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s
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@var32 = global i32 0
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@var64 = global i64 0
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define void @test_zr() {
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; CHECK-LABEL: test_zr:
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store i32 0, i32* @var32
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; CHECK: str wzr, [{{x[0-9]+}}, {{#?}}:lo12:var32]
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store i64 0, i64* @var64
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; CHECK: str xzr, [{{x[0-9]+}}, {{#?}}:lo12:var64]
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ret void
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; CHECK: ret
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}
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define void @test_sp(i32 %val) {
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; CHECK-LABEL: test_sp:
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; Important correctness point here is that LLVM doesn't try to use xzr
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; as an addressing register: "str w0, [xzr]" is not a valid A64
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; instruction (0b11111 in the Rn field would mean "sp").
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%addr = getelementptr i32, i32* null, i64 0
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store i32 %val, i32* %addr
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; CHECK: str {{w[0-9]+}}, [{{x[0-9]+|sp}}]
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ret void
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; CHECK: ret
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}
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declare i32 @bar()
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declare i32 @baz()
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; Check that the spill of the zero value gets stored directly instead
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; of being copied from wzr and then stored.
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define i32 @test_zr_spill_copyprop1(i1 %c) {
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; CHECK-LABEL: test_zr_spill_copyprop1:
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entry:
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br i1 %c, label %if.else, label %if.then
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if.else:
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; CHECK: bl bar
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; CHECK-NEXT: str w0, [sp, #[[SLOT:[0-9]+]]]
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%call1 = tail call i32 @bar()
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br label %if.end
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if.then:
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; CHECK: bl baz
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; CHECK-NEXT: str wzr, [sp, #[[SLOT]]]
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%call2 = tail call i32 @baz()
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br label %if.end
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if.end:
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%x.0 = phi i32 [ 0, %if.then ], [ %call1, %if.else ]
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call void asm sideeffect "", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{fp},~{lr},~{sp}"() nounwind
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ret i32 %x.0
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}
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; Similar to test_zr_spill_copyprop1, but with mis-matched register
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; class between %x.0 and the 0 from %if.then.
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define i32 @test_zr_spill_copyprop2(i1 %c) {
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; CHECK-LABEL: test_zr_spill_copyprop2:
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entry:
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br i1 %c, label %if.else, label %if.then
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if.else:
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; CHECK: bl bar
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; CHECK-NEXT: str w0, [sp, #[[SLOT:[0-9]+]]]
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%call1 = tail call i32 @bar()
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br label %if.end
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if.then:
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; CHECK: bl baz
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; CHECK-NEXT: str wzr, [sp, #[[SLOT]]]
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%call2 = tail call i32 @baz()
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br label %if.end
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if.end:
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%x.0 = phi i32 [ 0, %if.then ], [ %call1, %if.else ]
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call void asm sideeffect "", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{fp},~{lr},~{sp}"() nounwind
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%x.1 = add i32 %x.0, 1
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ret i32 %x.1
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}
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