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e9168c2be2
This was only added to preserve the old ScalarRepl's use of SSAUpdater which was originally to avoid use of dominance frontiers. Now, we only need a domtree, and we'll need a domtree right after this pass as well and so it makes perfect sense to always and only use the dom-tree powered mem2reg. This was flag-flipper earlier and has stuck reasonably so I wanted to gut the now-dead code out of SROA before we waste more time with it. Among other things, this will make passmanager porting easier. llvm-svn: 246028
237 lines
8.3 KiB
LLVM
237 lines
8.3 KiB
LLVM
; RUN: opt < %s -sroa -S | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
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define i8 @test1() {
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; We fully promote these to the i24 load or store size, resulting in just masks
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; and other operations that instcombine will fold, but no alloca. Note this is
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; the same as test12 in basictest.ll, but here we assert big-endian byte
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; ordering.
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;
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; CHECK-LABEL: @test1(
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entry:
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%a = alloca [3 x i8]
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%b = alloca [3 x i8]
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; CHECK-NOT: alloca
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%a0ptr = getelementptr [3 x i8], [3 x i8]* %a, i64 0, i32 0
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store i8 0, i8* %a0ptr
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%a1ptr = getelementptr [3 x i8], [3 x i8]* %a, i64 0, i32 1
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store i8 0, i8* %a1ptr
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%a2ptr = getelementptr [3 x i8], [3 x i8]* %a, i64 0, i32 2
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store i8 0, i8* %a2ptr
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%aiptr = bitcast [3 x i8]* %a to i24*
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%ai = load i24, i24* %aiptr
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; CHECK-NOT: store
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; CHECK-NOT: load
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; CHECK: %[[ext2:.*]] = zext i8 0 to i24
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; CHECK-NEXT: %[[mask2:.*]] = and i24 undef, -256
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; CHECK-NEXT: %[[insert2:.*]] = or i24 %[[mask2]], %[[ext2]]
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; CHECK-NEXT: %[[ext1:.*]] = zext i8 0 to i24
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; CHECK-NEXT: %[[shift1:.*]] = shl i24 %[[ext1]], 8
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; CHECK-NEXT: %[[mask1:.*]] = and i24 %[[insert2]], -65281
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; CHECK-NEXT: %[[insert1:.*]] = or i24 %[[mask1]], %[[shift1]]
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; CHECK-NEXT: %[[ext0:.*]] = zext i8 0 to i24
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; CHECK-NEXT: %[[shift0:.*]] = shl i24 %[[ext0]], 16
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; CHECK-NEXT: %[[mask0:.*]] = and i24 %[[insert1]], 65535
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; CHECK-NEXT: %[[insert0:.*]] = or i24 %[[mask0]], %[[shift0]]
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%biptr = bitcast [3 x i8]* %b to i24*
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store i24 %ai, i24* %biptr
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%b0ptr = getelementptr [3 x i8], [3 x i8]* %b, i64 0, i32 0
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%b0 = load i8, i8* %b0ptr
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%b1ptr = getelementptr [3 x i8], [3 x i8]* %b, i64 0, i32 1
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%b1 = load i8, i8* %b1ptr
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%b2ptr = getelementptr [3 x i8], [3 x i8]* %b, i64 0, i32 2
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%b2 = load i8, i8* %b2ptr
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; CHECK-NOT: store
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; CHECK-NOT: load
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; CHECK: %[[shift0:.*]] = lshr i24 %[[insert0]], 16
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; CHECK-NEXT: %[[trunc0:.*]] = trunc i24 %[[shift0]] to i8
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; CHECK-NEXT: %[[shift1:.*]] = lshr i24 %[[insert0]], 8
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; CHECK-NEXT: %[[trunc1:.*]] = trunc i24 %[[shift1]] to i8
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; CHECK-NEXT: %[[trunc2:.*]] = trunc i24 %[[insert0]] to i8
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%bsum0 = add i8 %b0, %b1
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%bsum1 = add i8 %bsum0, %b2
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ret i8 %bsum1
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; CHECK: %[[sum0:.*]] = add i8 %[[trunc0]], %[[trunc1]]
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; CHECK-NEXT: %[[sum1:.*]] = add i8 %[[sum0]], %[[trunc2]]
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; CHECK-NEXT: ret i8 %[[sum1]]
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}
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define i64 @test2() {
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; Test for various mixed sizes of integer loads and stores all getting
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; promoted.
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;
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; CHECK-LABEL: @test2(
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entry:
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%a = alloca [7 x i8]
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; CHECK-NOT: alloca
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%a0ptr = getelementptr [7 x i8], [7 x i8]* %a, i64 0, i32 0
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%a1ptr = getelementptr [7 x i8], [7 x i8]* %a, i64 0, i32 1
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%a2ptr = getelementptr [7 x i8], [7 x i8]* %a, i64 0, i32 2
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%a3ptr = getelementptr [7 x i8], [7 x i8]* %a, i64 0, i32 3
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; CHECK-NOT: store
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; CHECK-NOT: load
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%a0i16ptr = bitcast i8* %a0ptr to i16*
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store i16 1, i16* %a0i16ptr
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store i8 1, i8* %a2ptr
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; CHECK: %[[mask1:.*]] = and i40 undef, 4294967295
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; CHECK-NEXT: %[[insert1:.*]] = or i40 %[[mask1]], 4294967296
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%a3i24ptr = bitcast i8* %a3ptr to i24*
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store i24 1, i24* %a3i24ptr
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; CHECK-NEXT: %[[mask2:.*]] = and i40 %[[insert1]], -4294967041
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; CHECK-NEXT: %[[insert2:.*]] = or i40 %[[mask2]], 256
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%a2i40ptr = bitcast i8* %a2ptr to i40*
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store i40 1, i40* %a2i40ptr
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; CHECK-NEXT: %[[ext3:.*]] = zext i40 1 to i56
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; CHECK-NEXT: %[[mask3:.*]] = and i56 undef, -1099511627776
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; CHECK-NEXT: %[[insert3:.*]] = or i56 %[[mask3]], %[[ext3]]
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; CHECK-NOT: store
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; CHECK-NOT: load
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%aiptr = bitcast [7 x i8]* %a to i56*
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%ai = load i56, i56* %aiptr
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%ret = zext i56 %ai to i64
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ret i64 %ret
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; CHECK-NEXT: %[[ext4:.*]] = zext i16 1 to i56
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; CHECK-NEXT: %[[shift4:.*]] = shl i56 %[[ext4]], 40
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; CHECK-NEXT: %[[mask4:.*]] = and i56 %[[insert3]], 1099511627775
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; CHECK-NEXT: %[[insert4:.*]] = or i56 %[[mask4]], %[[shift4]]
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; CHECK-NEXT: %[[ret:.*]] = zext i56 %[[insert4]] to i64
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; CHECK-NEXT: ret i64 %[[ret]]
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}
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define i64 @PR14132(i1 %flag) {
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; CHECK-LABEL: @PR14132(
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; Here we form a PHI-node by promoting the pointer alloca first, and then in
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; order to promote the other two allocas, we speculate the load of the
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; now-phi-node-pointer. In doing so we end up loading a 64-bit value from an i8
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; alloca. While this is a bit dubious, we were asserting on trying to
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; rewrite it. The trick is that the code using the value may carefully take
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; steps to only use the not-undef bits, and so we need to at least loosely
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; support this. This test is particularly interesting because how we handle
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; a load of an i64 from an i8 alloca is dependent on endianness.
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entry:
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%a = alloca i64, align 8
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%b = alloca i8, align 8
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%ptr = alloca i64*, align 8
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; CHECK-NOT: alloca
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%ptr.cast = bitcast i64** %ptr to i8**
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store i64 0, i64* %a
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store i8 1, i8* %b
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store i64* %a, i64** %ptr
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br i1 %flag, label %if.then, label %if.end
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if.then:
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store i8* %b, i8** %ptr.cast
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br label %if.end
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; CHECK-NOT: store
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; CHECK: %[[ext:.*]] = zext i8 1 to i64
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; CHECK: %[[shift:.*]] = shl i64 %[[ext]], 56
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if.end:
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%tmp = load i64*, i64** %ptr
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%result = load i64, i64* %tmp
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; CHECK-NOT: load
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; CHECK: %[[result:.*]] = phi i64 [ %[[shift]], %if.then ], [ 0, %entry ]
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ret i64 %result
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; CHECK-NEXT: ret i64 %[[result]]
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}
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declare void @f(i64 %x, i32 %y)
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define void @test3() {
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; CHECK-LABEL: @test3(
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;
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; This is a test that specifically exercises the big-endian lowering because it
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; ends up splitting a 64-bit integer into two smaller integers and has a number
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; of tricky aspects (the i24 type) that make that hard. Historically, SROA
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; would miscompile this by either dropping a most significant byte or least
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; significant byte due to shrinking the [4,8) slice to an i24, or by failing to
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; move the bytes around correctly.
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;
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; The magical number 34494054408 is used because it has bits set in various
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; bytes so that it is clear if those bytes fail to be propagated.
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;
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; If you're debugging this, rather than using the direct magical numbers, run
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; the IR through '-sroa -instcombine'. With '-instcombine' these will be
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; constant folded, and if the i64 doesn't round-trip correctly, you've found
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; a bug!
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;
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entry:
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%a = alloca { i32, i24 }, align 4
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; CHECK-NOT: alloca
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%tmp0 = bitcast { i32, i24 }* %a to i64*
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store i64 34494054408, i64* %tmp0
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%tmp1 = load i64, i64* %tmp0, align 4
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%tmp2 = bitcast { i32, i24 }* %a to i32*
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%tmp3 = load i32, i32* %tmp2, align 4
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; CHECK: %[[HI_EXT:.*]] = zext i32 134316040 to i64
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; CHECK: %[[HI_INPUT:.*]] = and i64 undef, -4294967296
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; CHECK: %[[HI_MERGE:.*]] = or i64 %[[HI_INPUT]], %[[HI_EXT]]
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; CHECK: %[[LO_EXT:.*]] = zext i32 8 to i64
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; CHECK: %[[LO_SHL:.*]] = shl i64 %[[LO_EXT]], 32
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; CHECK: %[[LO_INPUT:.*]] = and i64 %[[HI_MERGE]], 4294967295
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; CHECK: %[[LO_MERGE:.*]] = or i64 %[[LO_INPUT]], %[[LO_SHL]]
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call void @f(i64 %tmp1, i32 %tmp3)
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; CHECK: call void @f(i64 %[[LO_MERGE]], i32 8)
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ret void
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; CHECK: ret void
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}
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define void @test4() {
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; CHECK-LABEL: @test4
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;
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; Much like @test3, this is specifically testing big-endian management of data.
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; Also similarly, it uses constants with particular bits set to help track
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; whether values are corrupted, and can be easily evaluated by running through
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; -instcombine to see that the i64 round-trips.
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;
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entry:
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%a = alloca { i32, i24 }, align 4
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%a2 = alloca i64, align 4
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; CHECK-NOT: alloca
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store i64 34494054408, i64* %a2
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%tmp0 = bitcast { i32, i24 }* %a to i8*
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%tmp1 = bitcast i64* %a2 to i8*
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp0, i8* %tmp1, i64 8, i32 4, i1 false)
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; CHECK: %[[LO_SHR:.*]] = lshr i64 34494054408, 32
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; CHECK: %[[LO_START:.*]] = trunc i64 %[[LO_SHR]] to i32
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; CHECK: %[[HI_START:.*]] = trunc i64 34494054408 to i32
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%tmp2 = bitcast { i32, i24 }* %a to i64*
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%tmp3 = load i64, i64* %tmp2, align 4
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%tmp4 = bitcast { i32, i24 }* %a to i32*
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%tmp5 = load i32, i32* %tmp4, align 4
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; CHECK: %[[HI_EXT:.*]] = zext i32 %[[HI_START]] to i64
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; CHECK: %[[HI_INPUT:.*]] = and i64 undef, -4294967296
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; CHECK: %[[HI_MERGE:.*]] = or i64 %[[HI_INPUT]], %[[HI_EXT]]
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; CHECK: %[[LO_EXT:.*]] = zext i32 %[[LO_START]] to i64
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; CHECK: %[[LO_SHL:.*]] = shl i64 %[[LO_EXT]], 32
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; CHECK: %[[LO_INPUT:.*]] = and i64 %[[HI_MERGE]], 4294967295
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; CHECK: %[[LO_MERGE:.*]] = or i64 %[[LO_INPUT]], %[[LO_SHL]]
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call void @f(i64 %tmp3, i32 %tmp5)
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; CHECK: call void @f(i64 %[[LO_MERGE]], i32 %[[LO_START]])
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ret void
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; CHECK: ret void
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}
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32, i1)
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