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209 lines
7.9 KiB
C++
209 lines
7.9 KiB
C++
//=== X86CallingConv.cpp - X86 Custom Calling Convention Impl -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the implementation of custom routines for the X86
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// Calling Convention that aren't done by tablegen.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/X86MCTargetDesc.h"
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#include "X86Subtarget.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/IR/CallingConv.h"
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namespace llvm {
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bool CC_X86_32_RegCall_Assign2Regs(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags, CCState &State) {
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// List of GPR registers that are available to store values in regcall
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// calling convention.
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static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI,
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X86::ESI};
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// The vector will save all the available registers for allocation.
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SmallVector<unsigned, 5> AvailableRegs;
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// searching for the available registers.
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for (auto Reg : RegList) {
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if (!State.isAllocated(Reg))
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AvailableRegs.push_back(Reg);
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}
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const size_t RequiredGprsUponSplit = 2;
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if (AvailableRegs.size() < RequiredGprsUponSplit)
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return false; // Not enough free registers - continue the search.
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// Allocating the available registers.
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for (unsigned I = 0; I < RequiredGprsUponSplit; I++) {
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// Marking the register as located.
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unsigned Reg = State.AllocateReg(AvailableRegs[I]);
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// Since we previously made sure that 2 registers are available
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// we expect that a real register number will be returned.
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assert(Reg && "Expecting a register will be available");
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// Assign the value to the allocated register
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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}
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// Successful in allocating regsiters - stop scanning next rules.
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return true;
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}
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static ArrayRef<MCPhysReg> CC_X86_VectorCallGetSSEs(const MVT &ValVT) {
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if (ValVT.is512BitVector()) {
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static const MCPhysReg RegListZMM[] = {X86::ZMM0, X86::ZMM1, X86::ZMM2,
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X86::ZMM3, X86::ZMM4, X86::ZMM5};
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return makeArrayRef(std::begin(RegListZMM), std::end(RegListZMM));
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}
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if (ValVT.is256BitVector()) {
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static const MCPhysReg RegListYMM[] = {X86::YMM0, X86::YMM1, X86::YMM2,
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X86::YMM3, X86::YMM4, X86::YMM5};
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return makeArrayRef(std::begin(RegListYMM), std::end(RegListYMM));
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}
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static const MCPhysReg RegListXMM[] = {X86::XMM0, X86::XMM1, X86::XMM2,
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X86::XMM3, X86::XMM4, X86::XMM5};
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return makeArrayRef(std::begin(RegListXMM), std::end(RegListXMM));
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}
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static ArrayRef<MCPhysReg> CC_X86_64_VectorCallGetGPRs() {
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static const MCPhysReg RegListGPR[] = {X86::RCX, X86::RDX, X86::R8, X86::R9};
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return makeArrayRef(std::begin(RegListGPR), std::end(RegListGPR));
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}
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static bool CC_X86_VectorCallAssignRegister(unsigned &ValNo, MVT &ValVT,
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MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags,
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CCState &State) {
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ArrayRef<MCPhysReg> RegList = CC_X86_VectorCallGetSSEs(ValVT);
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bool Is64bit = static_cast<const X86Subtarget &>(
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State.getMachineFunction().getSubtarget())
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.is64Bit();
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for (auto Reg : RegList) {
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// If the register is not marked as allocated - assign to it.
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if (!State.isAllocated(Reg)) {
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unsigned AssigedReg = State.AllocateReg(Reg);
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assert(AssigedReg == Reg && "Expecting a valid register allocation");
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State.addLoc(
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CCValAssign::getReg(ValNo, ValVT, AssigedReg, LocVT, LocInfo));
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return true;
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}
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// If the register is marked as shadow allocated - assign to it.
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if (Is64bit && State.IsShadowAllocatedReg(Reg)) {
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State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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return true;
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}
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}
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llvm_unreachable("Clang should ensure that hva marked vectors will have "
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"an available register.");
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return false;
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}
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bool CC_X86_64_VectorCall(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags, CCState &State) {
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// On the second pass, go through the HVAs only.
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if (ArgFlags.isSecArgPass()) {
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if (ArgFlags.isHva())
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return CC_X86_VectorCallAssignRegister(ValNo, ValVT, LocVT, LocInfo,
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ArgFlags, State);
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return true;
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}
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// Process only vector types as defined by vectorcall spec:
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// "A vector type is either a floating-point type, for example,
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// a float or double, or an SIMD vector type, for example, __m128 or __m256".
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if (!(ValVT.isFloatingPoint() ||
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(ValVT.isVector() && ValVT.getSizeInBits() >= 128))) {
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// If R9 was already assigned it means that we are after the fourth element
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// and because this is not an HVA / Vector type, we need to allocate
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// shadow XMM register.
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if (State.isAllocated(X86::R9)) {
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// Assign shadow XMM register.
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(void)State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT));
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}
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return false;
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}
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if (!ArgFlags.isHva() || ArgFlags.isHvaStart()) {
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// Assign shadow GPR register.
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(void)State.AllocateReg(CC_X86_64_VectorCallGetGPRs());
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// Assign XMM register - (shadow for HVA and non-shadow for non HVA).
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if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) {
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// In Vectorcall Calling convention, additional shadow stack can be
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// created on top of the basic 32 bytes of win64.
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// It can happen if the fifth or sixth argument is vector type or HVA.
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// At that case for each argument a shadow stack of 8 bytes is allocated.
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if (Reg == X86::XMM4 || Reg == X86::XMM5)
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State.AllocateStack(8, 8);
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if (!ArgFlags.isHva()) {
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State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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return true; // Allocated a register - Stop the search.
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}
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}
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}
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// If this is an HVA - Stop the search,
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// otherwise continue the search.
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return ArgFlags.isHva();
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}
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bool CC_X86_32_VectorCall(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags, CCState &State) {
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// On the second pass, go through the HVAs only.
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if (ArgFlags.isSecArgPass()) {
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if (ArgFlags.isHva())
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return CC_X86_VectorCallAssignRegister(ValNo, ValVT, LocVT, LocInfo,
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ArgFlags, State);
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return true;
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}
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// Process only vector types as defined by vectorcall spec:
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// "A vector type is either a floating point type, for example,
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// a float or double, or an SIMD vector type, for example, __m128 or __m256".
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if (!(ValVT.isFloatingPoint() ||
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(ValVT.isVector() && ValVT.getSizeInBits() >= 128))) {
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return false;
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}
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if (ArgFlags.isHva())
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return true; // If this is an HVA - Stop the search.
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// Assign XMM register.
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if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) {
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State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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return true;
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}
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// In case we did not find an available XMM register for a vector -
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// pass it indirectly.
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// It is similar to CCPassIndirect, with the addition of inreg.
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if (!ValVT.isFloatingPoint()) {
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LocVT = MVT::i32;
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LocInfo = CCValAssign::Indirect;
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ArgFlags.setInReg();
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}
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return false; // No register was assigned - Continue the search.
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}
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} // End llvm namespace
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