1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:23:23 +01:00
llvm-mirror/docs/GlobalISel
Amara Emerson bbd25a9a88 [GlobalISel] Add G_VECREDUCE_* opcodes for vector reductions.
These mirror the IR and SelectionDAG intrinsics & nodes.

Opcodes added:
G_VECREDUCE_SEQ_FADD
G_VECREDUCE_SEQ_FMUL
G_VECREDUCE_FADD
G_VECREDUCE_FMUL
G_VECREDUCE_FMAX
G_VECREDUCE_FMIN
G_VECREDUCE_ADD
G_VECREDUCE_MUL
G_VECREDUCE_AND
G_VECREDUCE_OR
G_VECREDUCE_XOR
G_VECREDUCE_SMAX
G_VECREDUCE_SMIN
G_VECREDUCE_UMAX
G_VECREDUCE_UMIN

Differential Revision: https://reviews.llvm.org/D88750
2020-10-08 10:33:19 -07:00
..
block-extract.png
GenericOpcode.rst [GlobalISel] Add G_VECREDUCE_* opcodes for vector reductions. 2020-10-08 10:33:19 -07:00
GMIR.rst [docs] Fix typos 2020-08-09 19:31:49 -07:00
index.rst
InstructionSelect.rst
IRTranslator.rst
KnownBits.rst
Legalizer.rst GlobalISel: Make type for lower action more consistently optional 2020-08-17 16:24:55 -04:00
pipeline-overview-customized.png
pipeline-overview-with-combiners.png
pipeline-overview.png
Pipeline.rst
Porting.rst
RegBankSelect.rst
Resources.rst
testing-pass-level.png
testing-unit-level.png