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5ef2195726
SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right instructions are still usable as zero and sign extensions. This adds new F3_Sr and F3_Si instruction formats that probably should be used for the 32-bit shifts as well. They don't really encode an simm13 field. llvm-svn: 178525
22 lines
370 B
LLVM
22 lines
370 B
LLVM
; RUN: llc < %s -march=sparcv9 | FileCheck %s
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; CHECK: ret2:
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; CHECK: or %g0, %i1, %i0
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define i64 @ret2(i64 %a, i64 %b) {
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ret i64 %b
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}
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; CHECK: shl_imm
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; CHECK: sllx %i0, 7, %i0
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define i64 @shl_imm(i64 %a) {
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%x = shl i64 %a, 7
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ret i64 %x
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}
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; CHECK: sra_reg
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; CHECK: srax %i0, %i1, %i0
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define i64 @sra_reg(i64 %a, i64 %b) {
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%x = ashr i64 %a, %b
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ret i64 %x
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}
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