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5efe040582
Initialize all AArch64-specific passes in the TargetMachine so they can be run by llc. This can lead to conflicts in opt with some command line options that share the same name as the pass, so I took this opportunity to do some cleanups: * rename all relevant command line options from "aarch64-blah" to "aarch64-enable-blah" and update the tests accordingly * run clang-format on their declarations * move all these declarations to a common place (the TargetMachine) as opposed to having them scattered around (AArch64BranchRelaxation and AArch64AddressTypePromotion were the only offenders) llvm-svn: 277322
132 lines
4.3 KiB
LLVM
132 lines
4.3 KiB
LLVM
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-enable-stp-suppress=false -verify-machineinstrs -mcpu=cyclone | FileCheck %s
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; CHECK-LABEL: stp_int
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; CHECK: stp w0, w1, [x2]
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define void @stp_int(i32 %a, i32 %b, i32* nocapture %p) nounwind {
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store i32 %a, i32* %p, align 4
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%add.ptr = getelementptr inbounds i32, i32* %p, i64 1
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store i32 %b, i32* %add.ptr, align 4
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ret void
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}
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; CHECK-LABEL: stp_long
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; CHECK: stp x0, x1, [x2]
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define void @stp_long(i64 %a, i64 %b, i64* nocapture %p) nounwind {
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store i64 %a, i64* %p, align 8
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%add.ptr = getelementptr inbounds i64, i64* %p, i64 1
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store i64 %b, i64* %add.ptr, align 8
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ret void
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}
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; CHECK-LABEL: stp_float
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; CHECK: stp s0, s1, [x0]
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define void @stp_float(float %a, float %b, float* nocapture %p) nounwind {
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store float %a, float* %p, align 4
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%add.ptr = getelementptr inbounds float, float* %p, i64 1
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store float %b, float* %add.ptr, align 4
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ret void
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}
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; CHECK-LABEL: stp_double
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; CHECK: stp d0, d1, [x0]
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define void @stp_double(double %a, double %b, double* nocapture %p) nounwind {
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store double %a, double* %p, align 8
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%add.ptr = getelementptr inbounds double, double* %p, i64 1
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store double %b, double* %add.ptr, align 8
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ret void
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}
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; Test the load/store optimizer---combine ldurs into a ldp, if appropriate
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define void @stur_int(i32 %a, i32 %b, i32* nocapture %p) nounwind {
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; CHECK-LABEL: stur_int
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; CHECK: stp w{{[0-9]+}}, {{w[0-9]+}}, [x{{[0-9]+}}, #-8]
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; CHECK-NEXT: ret
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%p1 = getelementptr inbounds i32, i32* %p, i32 -1
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store i32 %a, i32* %p1, align 2
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%p2 = getelementptr inbounds i32, i32* %p, i32 -2
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store i32 %b, i32* %p2, align 2
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ret void
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}
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define void @stur_long(i64 %a, i64 %b, i64* nocapture %p) nounwind {
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; CHECK-LABEL: stur_long
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; CHECK: stp x{{[0-9]+}}, {{x[0-9]+}}, [x{{[0-9]+}}, #-16]
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; CHECK-NEXT: ret
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%p1 = getelementptr inbounds i64, i64* %p, i32 -1
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store i64 %a, i64* %p1, align 2
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%p2 = getelementptr inbounds i64, i64* %p, i32 -2
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store i64 %b, i64* %p2, align 2
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ret void
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}
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define void @stur_float(float %a, float %b, float* nocapture %p) nounwind {
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; CHECK-LABEL: stur_float
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; CHECK: stp s{{[0-9]+}}, {{s[0-9]+}}, [x{{[0-9]+}}, #-8]
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; CHECK-NEXT: ret
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%p1 = getelementptr inbounds float, float* %p, i32 -1
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store float %a, float* %p1, align 2
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%p2 = getelementptr inbounds float, float* %p, i32 -2
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store float %b, float* %p2, align 2
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ret void
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}
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define void @stur_double(double %a, double %b, double* nocapture %p) nounwind {
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; CHECK-LABEL: stur_double
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; CHECK: stp d{{[0-9]+}}, {{d[0-9]+}}, [x{{[0-9]+}}, #-16]
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; CHECK-NEXT: ret
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%p1 = getelementptr inbounds double, double* %p, i32 -1
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store double %a, double* %p1, align 2
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%p2 = getelementptr inbounds double, double* %p, i32 -2
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store double %b, double* %p2, align 2
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ret void
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}
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define void @splat_v4i32(i32 %v, i32 *%p) {
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entry:
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; CHECK-LABEL: splat_v4i32
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; CHECK-DAG: stp w0, w0, [x1]
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; CHECK-DAG: stp w0, w0, [x1, #8]
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; CHECK: ret
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%p17 = insertelement <4 x i32> undef, i32 %v, i32 0
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%p18 = insertelement <4 x i32> %p17, i32 %v, i32 1
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%p19 = insertelement <4 x i32> %p18, i32 %v, i32 2
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%p20 = insertelement <4 x i32> %p19, i32 %v, i32 3
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%p21 = bitcast i32* %p to <4 x i32>*
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store <4 x i32> %p20, <4 x i32>* %p21, align 4
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ret void
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}
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; Read of %b to compute %tmp2 shouldn't prevent formation of stp
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; CHECK-LABEL: stp_int_rar_hazard
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; CHECK: ldr [[REG:w[0-9]+]], [x2, #8]
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; CHECK: add w8, [[REG]], w1
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; CHECK: stp w0, w1, [x2]
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; CHECK: ret
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define i32 @stp_int_rar_hazard(i32 %a, i32 %b, i32* nocapture %p) nounwind {
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store i32 %a, i32* %p, align 4
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%ld.ptr = getelementptr inbounds i32, i32* %p, i64 2
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%tmp = load i32, i32* %ld.ptr, align 4
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%tmp2 = add i32 %tmp, %b
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%add.ptr = getelementptr inbounds i32, i32* %p, i64 1
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store i32 %b, i32* %add.ptr, align 4
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ret i32 %tmp2
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}
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; Read of %b to compute %tmp2 shouldn't prevent formation of stp
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; CHECK-LABEL: stp_int_rar_hazard_after
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; CHECK: ldr [[REG:w[0-9]+]], [x3, #4]
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; CHECK: add w0, [[REG]], w2
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; CHECK: stp w1, w2, [x3]
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; CHECK: ret
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define i32 @stp_int_rar_hazard_after(i32 %w0, i32 %a, i32 %b, i32* nocapture %p) nounwind {
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store i32 %a, i32* %p, align 4
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%ld.ptr = getelementptr inbounds i32, i32* %p, i64 1
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%tmp = load i32, i32* %ld.ptr, align 4
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%tmp2 = add i32 %tmp, %b
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%add.ptr = getelementptr inbounds i32, i32* %p, i64 1
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store i32 %b, i32* %add.ptr, align 4
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ret i32 %tmp2
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}
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