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205 lines
10 KiB
TableGen
205 lines
10 KiB
TableGen
//===--- HexagonMapAsm2IntrinV62.gen.td -----------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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multiclass T_VR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VectorRegs:$src1, IntRegs:$src2),
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(MI VectorRegs:$src1, IntRegs:$src2)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, IntRegs:$src2),
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(!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, IntRegs:$src2)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_VVL_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegsLow8:$src3),
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(MI VectorRegs:$src1, VectorRegs:$src2, IntRegsLow8:$src3)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegsLow8:$src3),
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(!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegsLow8:$src3)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_VV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2),
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(MI VectorRegs:$src1, VectorRegs:$src2)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2),
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(!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_WW_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2),
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(MI VecDblRegs:$src1, VecDblRegs:$src2)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2),
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(!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_WVV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
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(MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3),
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(!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_WR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2),
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(MI VecDblRegs:$src1, IntRegs:$src2)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, IntRegs:$src2),
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(!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, IntRegs:$src2)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_WWR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3),
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(MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2, IntRegs:$src3),
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(!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2, IntRegs:$src3)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_VVR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
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(MI VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegs:$src3),
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(!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegs:$src3)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_ZR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VecPredRegs:$src1, IntRegs:$src2),
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(MI VecPredRegs:$src1, IntRegs:$src2)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1, IntRegs:$src2),
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(!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1, IntRegs:$src2)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_VZR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3),
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(MI VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VecPredRegs128B:$src2, IntRegs:$src3),
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(!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VecPredRegs128B:$src2, IntRegs:$src3)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_ZV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2),
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(MI VecPredRegs:$src1, VectorRegs:$src2)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1, VectorRegs128B:$src2),
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(!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1, VectorRegs128B:$src2)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_R_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID IntRegs:$src1),
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(MI IntRegs:$src1)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
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(!cast<InstHexagon>(MI#"_128B") IntRegs:$src1)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_ZZ_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VecPredRegs:$src1, VecPredRegs:$src2),
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(MI VecPredRegs:$src1, VecPredRegs:$src2)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1, VecPredRegs128B:$src2),
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(!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1, VecPredRegs128B:$src2)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_VVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, imm:$src3),
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(MI VectorRegs:$src1, VectorRegs:$src2, imm:$src3)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, imm:$src3),
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(!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, imm:$src3)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_VVVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4),
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(MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4),
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(!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_WVVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4),
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(MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4),
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(!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4)>,
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Requires<[UseHVXDbl]>;
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}
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def : T_R_pat <S6_vsplatrbp, int_hexagon_S6_vsplatrbp>;
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def : T_PP_pat <M6_vabsdiffb, int_hexagon_M6_vabsdiffb>;
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def : T_PP_pat <M6_vabsdiffub, int_hexagon_M6_vabsdiffub>;
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def : T_PP_pat <S6_vtrunehb_ppp, int_hexagon_S6_vtrunehb_ppp>;
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def : T_PP_pat <S6_vtrunohb_ppp, int_hexagon_S6_vtrunohb_ppp>;
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defm : T_VR_HVX_gen_pat <V6_vlsrb, int_hexagon_V6_vlsrb>;
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defm : T_VR_HVX_gen_pat <V6_vmpyiwub, int_hexagon_V6_vmpyiwub>;
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defm : T_VVL_HVX_gen_pat <V6_vasrwuhrndsat, int_hexagon_V6_vasrwuhrndsat>;
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defm : T_VVL_HVX_gen_pat <V6_vasruwuhrndsat, int_hexagon_V6_vasruwuhrndsat>;
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defm : T_VVL_HVX_gen_pat <V6_vasrhbsat, int_hexagon_V6_vasrhbsat>;
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defm : T_VVL_HVX_gen_pat <V6_vlutvvb_nm, int_hexagon_V6_vlutvvb_nm>;
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defm : T_VVL_HVX_gen_pat <V6_vlutvwh_nm, int_hexagon_V6_vlutvwh_nm>;
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defm : T_VV_HVX_gen_pat <V6_vrounduwuh, int_hexagon_V6_vrounduwuh>;
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defm : T_VV_HVX_gen_pat <V6_vrounduhub, int_hexagon_V6_vrounduhub>;
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defm : T_VV_HVX_gen_pat <V6_vadduwsat, int_hexagon_V6_vadduwsat>;
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defm : T_VV_HVX_gen_pat <V6_vsubuwsat, int_hexagon_V6_vsubuwsat>;
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defm : T_VV_HVX_gen_pat <V6_vaddbsat, int_hexagon_V6_vaddbsat>;
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defm : T_VV_HVX_gen_pat <V6_vsubbsat, int_hexagon_V6_vsubbsat>;
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defm : T_VV_HVX_gen_pat <V6_vaddububb_sat, int_hexagon_V6_vaddububb_sat>;
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defm : T_VV_HVX_gen_pat <V6_vsubububb_sat, int_hexagon_V6_vsubububb_sat>;
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defm : T_VV_HVX_gen_pat <V6_vmpyewuh_64, int_hexagon_V6_vmpyewuh_64>;
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defm : T_VV_HVX_gen_pat <V6_vmaxb, int_hexagon_V6_vmaxb>;
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defm : T_VV_HVX_gen_pat <V6_vminb, int_hexagon_V6_vminb>;
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defm : T_VV_HVX_gen_pat <V6_vsatuwuh, int_hexagon_V6_vsatuwuh>;
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defm : T_VV_HVX_gen_pat <V6_vaddclbw, int_hexagon_V6_vaddclbw>;
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defm : T_VV_HVX_gen_pat <V6_vaddclbh, int_hexagon_V6_vaddclbh>;
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defm : T_WW_HVX_gen_pat <V6_vadduwsat_dv, int_hexagon_V6_vadduwsat_dv>;
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defm : T_WW_HVX_gen_pat <V6_vsubuwsat_dv, int_hexagon_V6_vsubuwsat_dv>;
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defm : T_WW_HVX_gen_pat <V6_vaddbsat_dv, int_hexagon_V6_vaddbsat_dv>;
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defm : T_WW_HVX_gen_pat <V6_vsubbsat_dv, int_hexagon_V6_vsubbsat_dv>;
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defm : T_WVV_HVX_gen_pat <V6_vaddhw_acc, int_hexagon_V6_vaddhw_acc>;
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defm : T_WVV_HVX_gen_pat <V6_vadduhw_acc, int_hexagon_V6_vadduhw_acc>;
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defm : T_WVV_HVX_gen_pat <V6_vaddubh_acc, int_hexagon_V6_vaddubh_acc>;
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defm : T_WVV_HVX_gen_pat <V6_vmpyowh_64_acc, int_hexagon_V6_vmpyowh_64_acc>;
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defm : T_WR_HVX_gen_pat <V6_vmpauhb, int_hexagon_V6_vmpauhb>;
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defm : T_WWR_HVX_gen_pat <V6_vmpauhb_acc, int_hexagon_V6_vmpauhb_acc>;
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defm : T_VVR_HVX_gen_pat <V6_vmpyiwub_acc, int_hexagon_V6_vmpyiwub_acc>;
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defm : T_ZR_HVX_gen_pat <V6_vandnqrt, int_hexagon_V6_vandnqrt>;
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defm : T_VZR_HVX_gen_pat <V6_vandnqrt_acc, int_hexagon_V6_vandnqrt_acc>;
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defm : T_ZV_HVX_gen_pat <V6_vandvqv, int_hexagon_V6_vandvqv>;
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defm : T_ZV_HVX_gen_pat <V6_vandvnqv, int_hexagon_V6_vandvnqv>;
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defm : T_R_HVX_gen_pat <V6_pred_scalar2v2, int_hexagon_V6_pred_scalar2v2>;
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defm : T_R_HVX_gen_pat <V6_lvsplath, int_hexagon_V6_lvsplath>;
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defm : T_R_HVX_gen_pat <V6_lvsplatb, int_hexagon_V6_lvsplatb>;
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defm : T_ZZ_HVX_gen_pat <V6_shuffeqw, int_hexagon_V6_shuffeqw>;
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defm : T_ZZ_HVX_gen_pat <V6_shuffeqh, int_hexagon_V6_shuffeqh>;
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defm : T_VVI_HVX_gen_pat <V6_vlutvvbi, int_hexagon_V6_vlutvvbi>;
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defm : T_VVI_HVX_gen_pat <V6_vlutvwhi, int_hexagon_V6_vlutvwhi>;
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defm : T_VVVI_HVX_gen_pat <V6_vlutvvb_oracci, int_hexagon_V6_vlutvvb_oracci>;
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defm : T_WVVI_HVX_gen_pat <V6_vlutvwh_oracci, int_hexagon_V6_vlutvwh_oracci>;
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