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3708af1c59
really does need to be a vector type, because TargetLowering::getOperationAction for SIGN_EXTEND_INREG uses that type, and it needs to be able to distinguish between vectors and scalars. Also, fix some more issues with legalization of vector casts. llvm-svn: 93043
39 lines
938 B
LLVM
39 lines
938 B
LLVM
; RUN: llc < %s -march=x86-64
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; RUN: llc < %s -march=x86-64 -disable-mmx
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define <8 x i32> @a(<8 x i32> %a) nounwind {
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%b = trunc <8 x i32> %a to <8 x i16>
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%c = sext <8 x i16> %b to <8 x i32>
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ret <8 x i32> %c
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}
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define <3 x i32> @b(<3 x i32> %a) nounwind {
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%b = trunc <3 x i32> %a to <3 x i16>
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%c = sext <3 x i16> %b to <3 x i32>
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ret <3 x i32> %c
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}
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define <1 x i32> @c(<1 x i32> %a) nounwind {
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%b = trunc <1 x i32> %a to <1 x i16>
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%c = sext <1 x i16> %b to <1 x i32>
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ret <1 x i32> %c
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}
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define <8 x i32> @d(<8 x i32> %a) nounwind {
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%b = trunc <8 x i32> %a to <8 x i16>
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%c = zext <8 x i16> %b to <8 x i32>
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ret <8 x i32> %c
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}
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define <3 x i32> @e(<3 x i32> %a) nounwind {
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%b = trunc <3 x i32> %a to <3 x i16>
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%c = zext <3 x i16> %b to <3 x i32>
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ret <3 x i32> %c
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}
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define <1 x i32> @f(<1 x i32> %a) nounwind {
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%b = trunc <1 x i32> %a to <1 x i16>
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%c = zext <1 x i16> %b to <1 x i32>
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ret <1 x i32> %c
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}
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