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This patch adds a pipeline to support in-order CPUs such as ARM Cortex-A55. In-order pipeline implements a simplified version of Dispatch, Scheduler and Execute stages as a single stage. Entry and Retire stages are common for both in-order and out-of-order pipelines. Differential Revision: https://reviews.llvm.org/D94928 |
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bugpoint.rst | ||
dsymutil.rst | ||
FileCheck.rst | ||
index.rst | ||
lit.rst | ||
llc.rst | ||
lli.rst | ||
llvm-addr2line.rst | ||
llvm-ar.rst | ||
llvm-as.rst | ||
llvm-bcanalyzer.rst | ||
llvm-config.rst | ||
llvm-cov.rst | ||
llvm-cxxfilt.rst | ||
llvm-cxxmap.rst | ||
llvm-diff.rst | ||
llvm-dis.rst | ||
llvm-dwarfdump.rst | ||
llvm-exegesis-analysis.png | ||
llvm-exegesis.rst | ||
llvm-extract.rst | ||
llvm-install-name-tool.rst | ||
llvm-lib.rst | ||
llvm-libtool-darwin.rst | ||
llvm-link.rst | ||
llvm-lipo.rst | ||
llvm-locstats.rst | ||
llvm-mca.rst | ||
llvm-nm.rst | ||
llvm-objcopy.rst | ||
llvm-objdump.rst | ||
llvm-pdbutil.rst | ||
llvm-profdata.rst | ||
llvm-profgen.rst | ||
llvm-ranlib.rst | ||
llvm-readelf.rst | ||
llvm-readobj.rst | ||
llvm-size.rst | ||
llvm-stress.rst | ||
llvm-strings.rst | ||
llvm-strip.rst | ||
llvm-symbolizer.rst | ||
locstats-compare.png | ||
locstats-draw-plot.png | ||
opt.rst | ||
tblgen.rst |