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b5914c76cc
In PIC mode we were previously computing global variable addresses (or GOT entry addresses) by adding the PC, the PC-relative GOT displacement and the GOT-relative symbol/GOT entry displacement. Because the latter two displacements are fixed, we ended up performing one more addition than necessary. This change causes us to compute addresses using a single PC-relative displacement, resulting in a shorter code sequence. This reduces code size by about 4% in a recent build of Chromium for Android. As a result of this change we no longer need to compute the GOT base address in the ARM backend, which allows us to remove the Global Base Reg pass and SDAG lowering for the GOT. We also now no longer use the GOT when addressing a symbol which is known to be defined in the same linkage unit. Specifically, the symbol must have either hidden visibility or a strong definition in the current module in order to not use the the GOT. This is a change from the previous behaviour where we would use the GOT to address externally visible symbols defined in the same module. I think the only cases where this could matter are cases involving symbol interposition, but we don't really support that well anyway. Differential Revision: http://reviews.llvm.org/D13650 llvm-svn: 251322
135 lines
4.2 KiB
C++
135 lines
4.2 KiB
C++
//===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMInstrInfo.h"
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#include "ARM.h"
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#include "ARMConstantPoolValue.h"
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#include "ARMMachineFunctionInfo.h"
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#include "ARMTargetMachine.h"
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#include "MCTargetDesc/ARMAddressingModes.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/GlobalVariable.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCInst.h"
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using namespace llvm;
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ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
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: ARMBaseInstrInfo(STI), RI() {}
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/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
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void ARMInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
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if (hasNOP()) {
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NopInst.setOpcode(ARM::HINT);
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NopInst.addOperand(MCOperand::createImm(0));
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NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
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NopInst.addOperand(MCOperand::createReg(0));
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} else {
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NopInst.setOpcode(ARM::MOVr);
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NopInst.addOperand(MCOperand::createReg(ARM::R0));
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NopInst.addOperand(MCOperand::createReg(ARM::R0));
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NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
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NopInst.addOperand(MCOperand::createReg(0));
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NopInst.addOperand(MCOperand::createReg(0));
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}
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}
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unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
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switch (Opc) {
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default:
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break;
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case ARM::LDR_PRE_IMM:
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case ARM::LDR_PRE_REG:
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case ARM::LDR_POST_IMM:
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case ARM::LDR_POST_REG:
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return ARM::LDRi12;
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case ARM::LDRH_PRE:
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case ARM::LDRH_POST:
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return ARM::LDRH;
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case ARM::LDRB_PRE_IMM:
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case ARM::LDRB_PRE_REG:
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case ARM::LDRB_POST_IMM:
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case ARM::LDRB_POST_REG:
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return ARM::LDRBi12;
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case ARM::LDRSH_PRE:
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case ARM::LDRSH_POST:
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return ARM::LDRSH;
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case ARM::LDRSB_PRE:
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case ARM::LDRSB_POST:
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return ARM::LDRSB;
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case ARM::STR_PRE_IMM:
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case ARM::STR_PRE_REG:
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case ARM::STR_POST_IMM:
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case ARM::STR_POST_REG:
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return ARM::STRi12;
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case ARM::STRH_PRE:
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case ARM::STRH_POST:
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return ARM::STRH;
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case ARM::STRB_PRE_IMM:
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case ARM::STRB_PRE_REG:
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case ARM::STRB_POST_IMM:
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case ARM::STRB_POST_REG:
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return ARM::STRBi12;
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}
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return 0;
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}
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void ARMInstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI,
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Reloc::Model RM) const {
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MachineFunction &MF = *MI->getParent()->getParent();
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const ARMSubtarget &Subtarget = MF.getSubtarget<ARMSubtarget>();
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if (!Subtarget.useMovt(MF)) {
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if (RM == Reloc::PIC_)
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expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_pcrel, ARM::LDRi12, RM);
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else
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expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_abs, ARM::LDRi12, RM);
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return;
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}
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if (RM != Reloc::PIC_) {
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expandLoadStackGuardBase(MI, ARM::MOVi32imm, ARM::LDRi12, RM);
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return;
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}
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const GlobalValue *GV =
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cast<GlobalValue>((*MI->memoperands_begin())->getValue());
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if (!Subtarget.GVIsIndirectSymbol(GV, RM)) {
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expandLoadStackGuardBase(MI, ARM::MOV_ga_pcrel, ARM::LDRi12, RM);
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return;
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}
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MachineBasicBlock &MBB = *MI->getParent();
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DebugLoc DL = MI->getDebugLoc();
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unsigned Reg = MI->getOperand(0).getReg();
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MachineInstrBuilder MIB;
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MIB = BuildMI(MBB, MI, DL, get(ARM::MOV_ga_pcrel_ldr), Reg)
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.addGlobalAddress(GV, 0, ARMII::MO_NONLAZY);
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unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
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MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
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MachinePointerInfo::getGOT(*MBB.getParent()), Flag, 4, 4);
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MIB.addMemOperand(MMO);
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MIB = BuildMI(MBB, MI, DL, get(ARM::LDRi12), Reg);
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MIB.addReg(Reg, RegState::Kill).addImm(0);
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MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
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AddDefaultPred(MIB);
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}
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