mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-31 12:41:49 +01:00
beaa269335
Currently, instruction level fast math flags are not considered when
generating patterns for the machine combiner.
This currently leads to some missed opportunities to generate FMAs in
combination with `#pragma clang fp contract (fast)`.
For example, when building the example below with -O3 for AArch64, no
FMADD is generated. If built with -O2 and the DAGCombiner is used
instead of the MachineCombiner for FMAs, an FMADD is generated.
With this patch, the same code is generated in both cases.
float madd_contract(float a, float b, float c) {
#pragma clang fp contract (fast)
return (a * b) + c;
}
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D84930
400 lines
10 KiB
YAML
400 lines
10 KiB
YAML
# RUN: llc -run-pass=machine-combiner -o - -simplify-mir -mtriple=arm64-apple-iphoneos %s | FileCheck %s
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# Can create FMADD, because both the fmul and fadd have all fast-math flags.
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#
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# CHECK-LABEL: name: scalar_fmadd_fast
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# CHECK: [[C:%.*]]:fpr32 = COPY $s2
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# CHECK-NEXT: [[B:%.*]]:fpr32 = COPY $s1
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# CHECK-NEXT: [[A:%.*]]:fpr32 = COPY $s0
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# CHECK-NEXT: :fpr32 = FMADDSrrr [[B]], [[A]], [[C]]
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---
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name: scalar_fmadd_fast
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr32 }
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- { id: 1, class: fpr32 }
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- { id: 2, class: fpr32 }
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- { id: 3, class: fpr32 }
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- { id: 4, class: fpr32 }
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liveins:
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- { reg: '$s0', virtual-reg: '%0' }
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- { reg: '$s1', virtual-reg: '%1' }
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- { reg: '$s2', virtual-reg: '%2' }
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $s0, $s1, $s2
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%2:fpr32 = COPY $s2
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%1:fpr32 = COPY $s1
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%0:fpr32 = COPY $s0
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%3:fpr32 = nnan ninf nsz arcp contract afn reassoc FMULSrr %1, %0
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%4:fpr32 = nnan ninf nsz arcp contract afn reassoc FADDSrr killed %3, %2
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$s0 = COPY %4
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RET_ReallyLR implicit $s0
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...
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# Can create FMADD, because both the fmul and fadd have the contract fast-math flag.
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#
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# CHECK-LABEL: name: scalar_fmadd_contract
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# CHECK: [[C:%.*]]:fpr32 = COPY $s2
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# CHECK-NEXT: [[B:%.*]]:fpr32 = COPY $s1
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# CHECK-NEXT: [[A:%.*]]:fpr32 = COPY $s0
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# CHECK-NEXT: :fpr32 = FMADDSrrr [[B]], [[A]], [[C]]
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---
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name: scalar_fmadd_contract
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr32 }
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- { id: 1, class: fpr32 }
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- { id: 2, class: fpr32 }
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- { id: 3, class: fpr32 }
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- { id: 4, class: fpr32 }
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liveins:
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- { reg: '$s0', virtual-reg: '%0' }
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- { reg: '$s1', virtual-reg: '%1' }
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- { reg: '$s2', virtual-reg: '%2' }
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $s0, $s1, $s2
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%2:fpr32 = COPY $s2
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%1:fpr32 = COPY $s1
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%0:fpr32 = COPY $s0
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%3:fpr32 = contract FMULSrr %1, %0
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%4:fpr32 = contract FADDSrr killed %3, %2
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$s0 = COPY %4
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RET_ReallyLR implicit $s0
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...
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# Do not create FMADD, because we don't have the contract flag on the FADD.
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# CHECK-LABEL: name: scalar_fmadd_contract_op0
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# CHECK: [[C:%.*]]:fpr32 = COPY $s2
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# CHECK-NEXT: [[B:%.*]]:fpr32 = COPY $s1
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# CHECK-NEXT: [[A:%.*]]:fpr32 = COPY $s0
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# CHECK-NEXT: [[MUL:%.*]]:fpr32 = contract FMULSrr [[B]], [[A]]
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# CHECK-NEXT: fpr32 = FADDSrr killed [[MUL]], [[C]]
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---
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name: scalar_fmadd_contract_op0
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr32 }
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- { id: 1, class: fpr32 }
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- { id: 2, class: fpr32 }
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- { id: 3, class: fpr32 }
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- { id: 4, class: fpr32 }
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liveins:
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- { reg: '$s0', virtual-reg: '%0' }
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- { reg: '$s1', virtual-reg: '%1' }
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- { reg: '$s2', virtual-reg: '%2' }
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $s0, $s1, $s2
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%2:fpr32 = COPY $s2
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%1:fpr32 = COPY $s1
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%0:fpr32 = COPY $s0
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%3:fpr32 = contract FMULSrr %1, %0
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%4:fpr32 = FADDSrr killed %3, %2
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$s0 = COPY %4
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RET_ReallyLR implicit $s0
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...
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# Do create FMADD, because we have the contract flag on the FADD.
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#
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# CHECK-LABEL: name: scalar_fmadd_contract_op1
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# CHECK: [[C:%.*]]:fpr32 = COPY $s2
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# CHECK-NEXT: [[B:%.*]]:fpr32 = COPY $s1
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# CHECK-NEXT: [[A:%.*]]:fpr32 = COPY $s0
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# CHECK-NEXT: :fpr32 = FMADDSrrr [[B]], [[A]], [[C]]
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---
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name: scalar_fmadd_contract_op1
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr32 }
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- { id: 1, class: fpr32 }
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- { id: 2, class: fpr32 }
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- { id: 3, class: fpr32 }
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- { id: 4, class: fpr32 }
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liveins:
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- { reg: '$s0', virtual-reg: '%0' }
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- { reg: '$s1', virtual-reg: '%1' }
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- { reg: '$s2', virtual-reg: '%2' }
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $s0, $s1, $s2
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%2:fpr32 = COPY $s2
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%1:fpr32 = COPY $s1
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%0:fpr32 = COPY $s0
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%3:fpr32 = FMULSrr %1, %0
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%4:fpr32 = contract FADDSrr killed %3, %2
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$s0 = COPY %4
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RET_ReallyLR implicit $s0
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...
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# Do not create FMADD, as nsz flag does not allow it.
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#
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# CHECK-LABEL: name: scalar_fmadd_nsz
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# CHECK: [[C:%.*]]:fpr32 = COPY $s2
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# CHECK-NEXT: [[B:%.*]]:fpr32 = COPY $s1
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# CHECK-NEXT: [[A:%.*]]:fpr32 = COPY $s0
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# CHECK-NEXT: [[MUL:%.*]]:fpr32 = nsz FMULSrr [[B]], [[A]]
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# CHECK-NEXT: fpr32 = nsz FADDSrr killed [[MUL]], [[C]]
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---
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name: scalar_fmadd_nsz
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr32 }
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- { id: 1, class: fpr32 }
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- { id: 2, class: fpr32 }
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- { id: 3, class: fpr32 }
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- { id: 4, class: fpr32 }
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liveins:
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- { reg: '$s0', virtual-reg: '%0' }
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- { reg: '$s1', virtual-reg: '%1' }
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- { reg: '$s2', virtual-reg: '%2' }
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $s0, $s1, $s2
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%2:fpr32 = COPY $s2
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%1:fpr32 = COPY $s1
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%0:fpr32 = COPY $s0
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%3:fpr32 = nsz FMULSrr %1, %0
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%4:fpr32 = nsz FADDSrr killed %3, %2
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$s0 = COPY %4
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RET_ReallyLR implicit $s0
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...
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# Can create FMLA, because both the fmul and fadd have all fast-math flags.
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#
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# CHECK-LABEL: name: vector_fmadd_fast
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# CHECK: [[C:%.*]]:fpr128 = COPY $q2
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# CHECK-NEXT: [[B:%.*]]:fpr128 = COPY $q1
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# CHECK-NEXT: [[A:%.*]]:fpr128 = COPY $q0
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# CHECK-NEXT: fpr128 = FMLAv2f64 [[C]], [[B]], [[A]]
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---
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name: vector_fmadd_fast
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr128 }
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- { id: 1, class: fpr128 }
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- { id: 2, class: fpr128 }
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- { id: 3, class: fpr128 }
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- { id: 4, class: fpr128 }
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liveins:
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- { reg: '$q0', virtual-reg: '%0' }
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- { reg: '$q1', virtual-reg: '%1' }
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- { reg: '$q2', virtual-reg: '%2' }
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $q0, $q1, $q2
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%2:fpr128 = COPY $q2
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%1:fpr128 = COPY $q1
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%0:fpr128 = COPY $q0
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%3:fpr128 = nnan ninf nsz arcp contract afn reassoc FMULv2f64 %1, %0
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%4:fpr128 = nnan ninf nsz arcp contract afn reassoc FADDv2f64 killed %3, %2
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$q0 = COPY %4
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RET_ReallyLR implicit $q0
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...
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# Can create FMLA, because both the fmul and fadd have the contract fast-math flag.
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#
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# CHECK-LABEL: name: vector_fmadd_contract
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# CHECK: [[C:%.*]]:fpr128 = COPY $q2
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# CHECK-NEXT: [[B:%.*]]:fpr128 = COPY $q1
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# CHECK-NEXT: [[A:%.*]]:fpr128 = COPY $q0
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# CHECK-NEXT: fpr128 = FMLAv2f64 [[C]], [[B]], [[A]]
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---
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name: vector_fmadd_contract
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr128 }
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- { id: 1, class: fpr128 }
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- { id: 2, class: fpr128 }
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- { id: 3, class: fpr128 }
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- { id: 4, class: fpr128 }
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liveins:
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- { reg: '$q0', virtual-reg: '%0' }
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- { reg: '$q1', virtual-reg: '%1' }
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- { reg: '$q2', virtual-reg: '%2' }
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $q0, $q1, $q2
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%2:fpr128 = COPY $q2
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%1:fpr128 = COPY $q1
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%0:fpr128 = COPY $q0
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%3:fpr128 = contract FMULv2f64 %1, %0
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%4:fpr128 = contract FADDv2f64 killed %3, %2
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$q0 = COPY %4
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RET_ReallyLR implicit $q0
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...
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# Do not create FMLA, because we don't have the contract flag on the FADD.
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#
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# CHECK-LABEL: name: vector_fmadd_contract_op0
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# CHECK: [[C:%.*]]:fpr128 = COPY $q2
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# CHECK-NEXT: [[B:%.*]]:fpr128 = COPY $q1
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# CHECK-NEXT: [[A:%.*]]:fpr128 = COPY $q0
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# CHECK-NEXT: [[MUL:%.*]]:fpr128 = contract FMULv2f64 [[B]], [[A]]
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# CHECK-NEXT: fpr128 = FADDv2f64 killed [[MUL]], [[C]]
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---
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name: vector_fmadd_contract_op0
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr128 }
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- { id: 1, class: fpr128 }
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- { id: 2, class: fpr128 }
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- { id: 3, class: fpr128 }
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- { id: 4, class: fpr128 }
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liveins:
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- { reg: '$q0', virtual-reg: '%0' }
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- { reg: '$q1', virtual-reg: '%1' }
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- { reg: '$q2', virtual-reg: '%2' }
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $q0, $q1, $q2
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%2:fpr128 = COPY $q2
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%1:fpr128 = COPY $q1
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%0:fpr128 = COPY $q0
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%3:fpr128 = contract FMULv2f64 %1, %0
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%4:fpr128 = FADDv2f64 killed %3, %2
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$q0 = COPY %4
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RET_ReallyLR implicit $q0
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...
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# Do create FMLA, because we have the contract flag on the FADD.
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#
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# CHECK-LABEL: name: vector_fmadd_contract_op1
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# CHECK: [[C:%.*]]:fpr128 = COPY $q2
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# CHECK-NEXT: [[B:%.*]]:fpr128 = COPY $q1
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# CHECK-NEXT: [[A:%.*]]:fpr128 = COPY $q0
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# CHECK-NEXT: fpr128 = FMLAv2f64 [[C]], [[B]], [[A]]
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---
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name: vector_fmadd_contract_op1
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr128 }
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- { id: 1, class: fpr128 }
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- { id: 2, class: fpr128 }
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- { id: 3, class: fpr128 }
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- { id: 4, class: fpr128 }
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liveins:
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- { reg: '$q0', virtual-reg: '%0' }
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- { reg: '$q1', virtual-reg: '%1' }
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- { reg: '$q2', virtual-reg: '%2' }
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $q0, $q1, $q2
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%2:fpr128 = COPY $q2
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%1:fpr128 = COPY $q1
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%0:fpr128 = COPY $q0
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%3:fpr128 = FMULv2f64 %1, %0
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%4:fpr128 = contract FADDv2f64 killed %3, %2
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$q0 = COPY %4
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RET_ReallyLR implicit $q0
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...
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# Do not create FMLA, as nsz flag does not allow it.
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#
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# CHECK-LABEL: name: vector_fmadd_nsz
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# CHECK: [[C:%.*]]:fpr128 = COPY $q2
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# CHECK-NEXT: [[B:%.*]]:fpr128 = COPY $q1
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# CHECK-NEXT: [[A:%.*]]:fpr128 = COPY $q0
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# CHECK-NEXT: [[MUL:%.*]]:fpr128 = nsz FMULv2f64 [[B]], [[A]]
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# CHECK-NEXT: fpr128 = nsz FADDv2f64 killed [[MUL]], [[C]]
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---
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name: vector_fmadd_nsz
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr128 }
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- { id: 1, class: fpr128 }
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- { id: 2, class: fpr128 }
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- { id: 3, class: fpr128 }
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- { id: 4, class: fpr128 }
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liveins:
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- { reg: '$q0', virtual-reg: '%0' }
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- { reg: '$q1', virtual-reg: '%1' }
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- { reg: '$q2', virtual-reg: '%2' }
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $q0, $q1, $q2
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%2:fpr128 = COPY $q2
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%1:fpr128 = COPY $q1
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%0:fpr128 = COPY $q0
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%3:fpr128 = nsz FMULv2f64 %1, %0
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%4:fpr128 = nsz FADDv2f64 killed %3, %2
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$q0 = COPY %4
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RET_ReallyLR implicit $q0
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...
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