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I have added a new file: llvm/test/CodeGen/AArch64/README that describes what to do in the event one of the SVE codegen tests fails the warnings check. In addition, I've added comments to all the relevant SVE tests pointing users at the README file. Differential Revision: https://reviews.llvm.org/D83467
262 lines
7.9 KiB
LLVM
262 lines
7.9 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -asm-verbose=0 < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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; Since UQDEC{B|H|W|D|P} and UQINC{B|H|W|D|P} have identical semantics, the tests for
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; * @llvm.aarch64.sve.uqinc{b|h|w|d|p}, and
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; * @llvm.aarch64.sve.uqdec{b|h|w|d|p}
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; should also be identical (with the instruction name being adjusted). When
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; updating this file remember to make similar changes in the file testing the
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; other intrinsic.
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;
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; UQINCH (vector)
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;
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define <vscale x 8 x i16> @uqinch(<vscale x 8 x i16> %a) {
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; CHECK-LABEL: uqinch:
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; CHECK: uqinch z0.h, pow2
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqinch.nxv8i16(<vscale x 8 x i16> %a,
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i32 0, i32 1)
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ret <vscale x 8 x i16> %out
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}
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;
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; UQINCW (vector)
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;
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define <vscale x 4 x i32> @uqincw(<vscale x 4 x i32> %a) {
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; CHECK-LABEL: uqincw:
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; CHECK: uqincw z0.s, vl1, mul #2
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqincw.nxv4i32(<vscale x 4 x i32> %a,
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i32 1, i32 2)
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ret <vscale x 4 x i32> %out
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}
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;
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; UQINCD (vector)
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;
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define <vscale x 2 x i64> @uqincd(<vscale x 2 x i64> %a) {
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; CHECK-LABEL: uqincd:
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; CHECK: uqincd z0.d, vl2, mul #3
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqincd.nxv2i64(<vscale x 2 x i64> %a,
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i32 2, i32 3)
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ret <vscale x 2 x i64> %out
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}
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;
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; UQINCP (vector)
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;
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define <vscale x 8 x i16> @uqincp_b16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %b) {
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; CHECK-LABEL: uqincp_b16:
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; CHECK: uqincp z0.h, p0
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqincp.nxv8i16(<vscale x 8 x i16> %a,
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<vscale x 8 x i1> %b)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @uqincp_b32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b) {
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; CHECK-LABEL: uqincp_b32:
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; CHECK: uqincp z0.s, p0
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqincp.nxv4i32(<vscale x 4 x i32> %a,
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<vscale x 4 x i1> %b)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @uqincp_b64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %b) {
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; CHECK-LABEL: uqincp_b64:
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; CHECK: uqincp z0.d, p0
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqincp.nxv2i64(<vscale x 2 x i64> %a,
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<vscale x 2 x i1> %b)
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ret <vscale x 2 x i64> %out
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}
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;
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; UQINCB (scalar)
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;
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define i32 @uqincb_n32(i32 %a) {
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; CHECK-LABEL: uqincb_n32:
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; CHECK: uqincb w0, vl3, mul #4
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; CHECK-NEXT: ret
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%out = call i32 @llvm.aarch64.sve.uqincb.n32(i32 %a, i32 3, i32 4)
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ret i32 %out
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}
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define i64 @uqincb_n64(i64 %a) {
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; CHECK-LABEL: uqincb_n64:
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; CHECK: uqincb x0, vl4, mul #5
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; CHECK-NEXT: ret
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%out = call i64 @llvm.aarch64.sve.uqincb.n64(i64 %a, i32 4, i32 5)
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ret i64 %out
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}
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;
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; UQINCH (scalar)
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;
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define i32 @uqinch_n32(i32 %a) {
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; CHECK-LABEL: uqinch_n32:
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; CHECK: uqinch w0, vl5, mul #6
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; CHECK-NEXT: ret
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%out = call i32 @llvm.aarch64.sve.uqinch.n32(i32 %a, i32 5, i32 6)
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ret i32 %out
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}
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define i64 @uqinch_n64(i64 %a) {
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; CHECK-LABEL: uqinch_n64:
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; CHECK: uqinch x0, vl6, mul #7
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; CHECK-NEXT: ret
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%out = call i64 @llvm.aarch64.sve.uqinch.n64(i64 %a, i32 6, i32 7)
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ret i64 %out
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}
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;
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; UQINCW (scalar)
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;
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define i32 @uqincw_n32(i32 %a) {
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; CHECK-LABEL: uqincw_n32:
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; CHECK: uqincw w0, vl7, mul #8
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; CHECK-NEXT: ret
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%out = call i32 @llvm.aarch64.sve.uqincw.n32(i32 %a, i32 7, i32 8)
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ret i32 %out
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}
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define i64 @uqincw_n64(i64 %a) {
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; CHECK-LABEL: uqincw_n64:
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; CHECK: uqincw x0, vl8, mul #9
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; CHECK-NEXT: ret
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%out = call i64 @llvm.aarch64.sve.uqincw.n64(i64 %a, i32 8, i32 9)
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ret i64 %out
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}
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;
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; UQINCD (scalar)
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;
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define i32 @uqincd_n32(i32 %a) {
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; CHECK-LABEL: uqincd_n32:
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; CHECK: uqincd w0, vl16, mul #10
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; CHECK-NEXT: ret
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%out = call i32 @llvm.aarch64.sve.uqincd.n32(i32 %a, i32 9, i32 10)
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ret i32 %out
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}
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define i64 @uqincd_n64(i64 %a) {
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; CHECK-LABEL: uqincd_n64:
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; CHECK: uqincd x0, vl32, mul #11
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; CHECK-NEXT: ret
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%out = call i64 @llvm.aarch64.sve.uqincd.n64(i64 %a, i32 10, i32 11)
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ret i64 %out
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}
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;
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; UQINCP (scalar)
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;
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define i32 @uqincp_n32_b8(i32 %a, <vscale x 16 x i1> %b) {
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; CHECK-LABEL: uqincp_n32_b8:
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; CHECK: uqincp w0, p0.b
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; CHECK-NEXT: ret
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%out = call i32 @llvm.aarch64.sve.uqincp.n32.nxv16i1(i32 %a, <vscale x 16 x i1> %b)
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ret i32 %out
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}
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define i32 @uqincp_n32_b16(i32 %a, <vscale x 8 x i1> %b) {
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; CHECK-LABEL: uqincp_n32_b16:
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; CHECK: uqincp w0, p0.h
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; CHECK-NEXT: ret
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%out = call i32 @llvm.aarch64.sve.uqincp.n32.nxv8i1(i32 %a, <vscale x 8 x i1> %b)
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ret i32 %out
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}
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define i32 @uqincp_n32_b32(i32 %a, <vscale x 4 x i1> %b) {
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; CHECK-LABEL: uqincp_n32_b32:
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; CHECK: uqincp w0, p0.s
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; CHECK-NEXT: ret
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%out = call i32 @llvm.aarch64.sve.uqincp.n32.nxv4i1(i32 %a, <vscale x 4 x i1> %b)
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ret i32 %out
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}
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define i32 @uqincp_n32_b64(i32 %a, <vscale x 2 x i1> %b) {
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; CHECK-LABEL: uqincp_n32_b64:
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; CHECK: uqincp w0, p0.d
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; CHECK-NEXT: ret
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%out = call i32 @llvm.aarch64.sve.uqincp.n32.nxv2i1(i32 %a, <vscale x 2 x i1> %b)
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ret i32 %out
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}
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define i64 @uqincp_n64_b8(i64 %a, <vscale x 16 x i1> %b) {
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; CHECK-LABEL: uqincp_n64_b8:
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; CHECK: uqincp x0, p0.b
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; CHECK-NEXT: ret
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%out = call i64 @llvm.aarch64.sve.uqincp.n64.nxv16i1(i64 %a, <vscale x 16 x i1> %b)
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ret i64 %out
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}
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define i64 @uqincp_n64_b16(i64 %a, <vscale x 8 x i1> %b) {
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; CHECK-LABEL: uqincp_n64_b16:
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; CHECK: uqincp x0, p0.h
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; CHECK-NEXT: ret
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%out = call i64 @llvm.aarch64.sve.uqincp.n64.nxv8i1(i64 %a, <vscale x 8 x i1> %b)
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ret i64 %out
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}
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define i64 @uqincp_n64_b32(i64 %a, <vscale x 4 x i1> %b) {
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; CHECK-LABEL: uqincp_n64_b32:
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; CHECK: uqincp x0, p0.s
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; CHECK-NEXT: ret
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%out = call i64 @llvm.aarch64.sve.uqincp.n64.nxv4i1(i64 %a, <vscale x 4 x i1> %b)
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ret i64 %out
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}
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define i64 @uqincp_n64_b64(i64 %a, <vscale x 2 x i1> %b) {
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; CHECK-LABEL: uqincp_n64_b64:
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; CHECK: uqincp x0, p0.d
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; CHECK-NEXT: ret
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%out = call i64 @llvm.aarch64.sve.uqincp.n64.nxv2i1(i64 %a, <vscale x 2 x i1> %b)
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ret i64 %out
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}
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; uqinc{h|w|d}(vector, pattern, multiplier)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.uqinch.nxv8i16(<vscale x 8 x i16>, i32, i32)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.uqincw.nxv4i32(<vscale x 4 x i32>, i32, i32)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.uqincd.nxv2i64(<vscale x 2 x i64>, i32, i32)
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; uqinc{b|h|w|d}(scalar, pattern, multiplier)
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declare i32 @llvm.aarch64.sve.uqincb.n32(i32, i32, i32)
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declare i64 @llvm.aarch64.sve.uqincb.n64(i64, i32, i32)
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declare i32 @llvm.aarch64.sve.uqinch.n32(i32, i32, i32)
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declare i64 @llvm.aarch64.sve.uqinch.n64(i64, i32, i32)
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declare i32 @llvm.aarch64.sve.uqincw.n32(i32, i32, i32)
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declare i64 @llvm.aarch64.sve.uqincw.n64(i64, i32, i32)
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declare i32 @llvm.aarch64.sve.uqincd.n32(i32, i32, i32)
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declare i64 @llvm.aarch64.sve.uqincd.n64(i64, i32, i32)
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; uqincp(scalar, predicate)
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declare i32 @llvm.aarch64.sve.uqincp.n32.nxv16i1(i32, <vscale x 16 x i1>)
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declare i32 @llvm.aarch64.sve.uqincp.n32.nxv8i1(i32, <vscale x 8 x i1>)
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declare i32 @llvm.aarch64.sve.uqincp.n32.nxv4i1(i32, <vscale x 4 x i1>)
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declare i32 @llvm.aarch64.sve.uqincp.n32.nxv2i1(i32, <vscale x 2 x i1>)
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declare i64 @llvm.aarch64.sve.uqincp.n64.nxv16i1(i64, <vscale x 16 x i1>)
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declare i64 @llvm.aarch64.sve.uqincp.n64.nxv8i1(i64, <vscale x 8 x i1>)
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declare i64 @llvm.aarch64.sve.uqincp.n64.nxv4i1(i64, <vscale x 4 x i1>)
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declare i64 @llvm.aarch64.sve.uqincp.n64.nxv2i1(i64, <vscale x 2 x i1>)
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; uqincp(vector, predicate)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.uqincp.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.uqincp.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.uqincp.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>)
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