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https://github.com/RPCS3/llvm-mirror.git
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30eb603e95
Summary: This patch modifies IncrementMemoryAddress to use a vscale when calculating the new address if the data type is scalable. Also adds tablegen patterns which match an extract_subvector of a legal predicate type with zip1/zip2 instructions Reviewers: sdesmalen, efriedma, david-arm Reviewed By: efriedma, david-arm Subscribers: tschuett, hiraditya, psnobl, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D83137
135 lines
5.2 KiB
LLVM
135 lines
5.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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; UNPREDICATED
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define void @store_promote_4i8(<vscale x 4 x i8> %data, <vscale x 4 x i8>* %a) {
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; CHECK-LABEL: store_promote_4i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: st1b { z0.s }, p0, [x0]
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; CHECK-NEXT: ret
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store <vscale x 4 x i8> %data, <vscale x 4 x i8>* %a
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ret void
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}
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define void @store_split_i16(<vscale x 16 x i16> %data, <vscale x 16 x i16>* %a) {
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; CHECK-LABEL: store_split_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: st1h { z1.h }, p0, [x0, #1, mul vl]
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; CHECK-NEXT: st1h { z0.h }, p0, [x0]
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; CHECK-NEXT: ret
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store <vscale x 16 x i16> %data, <vscale x 16 x i16>* %a
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ret void
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}
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define void @store_split_16i32(<vscale x 16 x i32> %data, <vscale x 16 x i32>* %a) {
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; CHECK-LABEL: store_split_16i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: st1w { z3.s }, p0, [x0, #3, mul vl]
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; CHECK-NEXT: st1w { z2.s }, p0, [x0, #2, mul vl]
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; CHECK-NEXT: st1w { z1.s }, p0, [x0, #1, mul vl]
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; CHECK-NEXT: st1w { z0.s }, p0, [x0]
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; CHECK-NEXT: ret
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store <vscale x 16 x i32> %data, <vscale x 16 x i32>* %a
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ret void
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}
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define void @store_split_16i64(<vscale x 16 x i64> %data, <vscale x 16 x i64>* %a) {
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; CHECK-LABEL: store_split_16i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: st1d { z7.d }, p0, [x0, #7, mul vl]
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; CHECK-NEXT: st1d { z6.d }, p0, [x0, #6, mul vl]
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; CHECK-NEXT: st1d { z5.d }, p0, [x0, #5, mul vl]
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; CHECK-NEXT: st1d { z4.d }, p0, [x0, #4, mul vl]
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; CHECK-NEXT: st1d { z3.d }, p0, [x0, #3, mul vl]
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; CHECK-NEXT: st1d { z2.d }, p0, [x0, #2, mul vl]
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; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl]
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; CHECK-NEXT: st1d { z0.d }, p0, [x0]
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; CHECK-NEXT: ret
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store <vscale x 16 x i64> %data, <vscale x 16 x i64>* %a
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ret void
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}
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; MASKED
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define void @masked_store_promote_2i8(<vscale x 2 x i8> %data, <vscale x 2 x i8> *%a, <vscale x 2 x i1> %pg) {
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; CHECK-LABEL: masked_store_promote_2i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: st1b { z0.d }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.masked.store.nxv2i8(<vscale x 2 x i8> %data, <vscale x 2 x i8> *%a, i32 1, <vscale x 2 x i1> %pg)
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ret void
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}
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define void @masked_store_split_32i8(<vscale x 32 x i8> %data, <vscale x 32 x i8> *%a, <vscale x 32 x i1> %pg) {
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; CHECK-LABEL: masked_store_split_32i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: st1b { z1.b }, p1, [x0, #1, mul vl]
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; CHECK-NEXT: st1b { z0.b }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.masked.store.nxv32i8(<vscale x 32 x i8> %data, <vscale x 32 x i8> *%a, i32 1, <vscale x 32 x i1> %pg)
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ret void
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}
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define void @masked_store_split_32i16(<vscale x 32 x i16> %data, <vscale x 32 x i16> *%a, <vscale x 32 x i1> %pg) {
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; CHECK-LABEL: masked_store_split_32i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: pfalse p2.b
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; CHECK-NEXT: zip2 p3.b, p1.b, p2.b
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; CHECK-NEXT: zip1 p1.b, p1.b, p2.b
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; CHECK-NEXT: st1h { z3.h }, p3, [x0, #3, mul vl]
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; CHECK-NEXT: zip2 p3.b, p0.b, p2.b
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; CHECK-NEXT: zip1 p0.b, p0.b, p2.b
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; CHECK-NEXT: st1h { z2.h }, p1, [x0, #2, mul vl]
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; CHECK-NEXT: st1h { z1.h }, p3, [x0, #1, mul vl]
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; CHECK-NEXT: st1h { z0.h }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.masked.store.nxv32i16(<vscale x 32 x i16> %data, <vscale x 32 x i16> *%a, i32 1, <vscale x 32 x i1> %pg)
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ret void
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}
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define void @masked_store_split_8i32(<vscale x 8 x i32> %data, <vscale x 8 x i32> *%a, <vscale x 8 x i1> %pg) {
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; CHECK-LABEL: masked_store_split_8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: pfalse p1.b
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; CHECK-NEXT: zip2 p2.h, p0.h, p1.h
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; CHECK-NEXT: zip1 p0.h, p0.h, p1.h
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; CHECK-NEXT: st1w { z1.s }, p2, [x0, #1, mul vl]
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; CHECK-NEXT: st1w { z0.s }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.masked.store.nxv8i32(<vscale x 8 x i32> %data, <vscale x 8 x i32> *%a, i32 1, <vscale x 8 x i1> %pg)
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ret void
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}
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define void @masked_store_split_8i64(<vscale x 8 x i64> %data, <vscale x 8 x i64> *%a, <vscale x 8 x i1> %pg) {
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; CHECK-LABEL: masked_store_split_8i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: pfalse p1.b
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; CHECK-NEXT: zip2 p2.h, p0.h, p1.h
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; CHECK-NEXT: zip1 p0.h, p0.h, p1.h
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; CHECK-NEXT: zip2 p3.s, p2.s, p1.s
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; CHECK-NEXT: zip1 p2.s, p2.s, p1.s
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; CHECK-NEXT: st1d { z2.d }, p2, [x0, #2, mul vl]
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; CHECK-NEXT: zip2 p2.s, p0.s, p1.s
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; CHECK-NEXT: zip1 p0.s, p0.s, p1.s
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; CHECK-NEXT: st1d { z3.d }, p3, [x0, #3, mul vl]
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; CHECK-NEXT: st1d { z1.d }, p2, [x0, #1, mul vl]
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; CHECK-NEXT: st1d { z0.d }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.masked.store.nxv8i64(<vscale x 8 x i64> %data, <vscale x 8 x i64> *%a, i32 1, <vscale x 8 x i1> %pg)
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ret void
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}
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declare void @llvm.masked.store.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>*, i32, <vscale x 2 x i1>)
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declare void @llvm.masked.store.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>*, i32, <vscale x 32 x i1>)
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declare void @llvm.masked.store.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>*, i32, <vscale x 32 x i1>)
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declare void @llvm.masked.store.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>*, i32, <vscale x 8 x i1>)
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declare void @llvm.masked.store.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>*, i32, <vscale x 8 x i1>)
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