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https://github.com/RPCS3/llvm-mirror.git
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6a9013112e
This patch changes the FP conversion intrinsics to take a predicate that matches the number of lanes for the vector with the widest element type as opposed to using <vscale x 16 x i1>. For example: ```<vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f16(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 8 x half>)``` now uses <vscale x 4 x i1> instead of <vscale x 16 x i1> And similar for: ```<vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f64(<vscale x 4 x float>, <vscale x 2 x i1>, <vscale x 2 x double>)``` where the predicate now matches the wider type, so <vscale x 2 x i1>. Reviewers: efriedma, SjoerdMeijer, paulwalker-arm, rengolin Reviewed By: efriedma Tags: #clang Differential Revision: https://reviews.llvm.org/D78402
85 lines
3.8 KiB
LLVM
85 lines
3.8 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
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;
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; FCVTLT
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;
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define <vscale x 4 x float> @fcvtlt_f32_f16(<vscale x 4 x float> %a, <vscale x 4 x i1> %pg, <vscale x 8 x half> %b) {
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; CHECK-LABEL: fcvtlt_f32_f16:
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; CHECK: fcvtlt z0.s, p0/m, z1.h
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtlt.f32f16(<vscale x 4 x float> %a,
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<vscale x 4 x i1> %pg,
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<vscale x 8 x half> %b)
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ret <vscale x 4 x float> %out
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}
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define <vscale x 2 x double> @fcvtlt_f64_f32(<vscale x 2 x double> %a, <vscale x 2 x i1> %pg, <vscale x 4 x float> %b) {
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; CHECK-LABEL: fcvtlt_f64_f32:
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; CHECK: fcvtlt z0.d, p0/m, z1.s
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x double> @llvm.aarch64.sve.fcvtlt.f64f32(<vscale x 2 x double> %a,
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<vscale x 2 x i1> %pg,
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<vscale x 4 x float> %b)
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ret <vscale x 2 x double> %out
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}
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;
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; FCVTNT
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;
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define <vscale x 8 x half> @fcvtnt_f16_f32(<vscale x 8 x half> %a, <vscale x 4 x i1> %pg, <vscale x 4 x float> %b) {
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; CHECK-LABEL: fcvtnt_f16_f32:
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; CHECK: fcvtnt z0.h, p0/m, z1.s
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x half> @llvm.aarch64.sve.fcvtnt.f16f32(<vscale x 8 x half> %a,
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<vscale x 4 x i1> %pg,
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<vscale x 4 x float> %b)
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ret <vscale x 8 x half> %out
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}
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define <vscale x 4 x float> @fcvtnt_f32_f64(<vscale x 4 x float> %a, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b) {
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; CHECK-LABEL: fcvtnt_f32_f64:
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; CHECK: fcvtnt z0.s, p0/m, z1.d
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtnt.f32f64(<vscale x 4 x float> %a,
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<vscale x 2 x i1> %pg,
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<vscale x 2 x double> %b)
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ret <vscale x 4 x float> %out
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}
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;
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; FCVTX
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;
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define <vscale x 4 x float> @fcvtx_f32_f64(<vscale x 4 x float> %a, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b) {
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; CHECK-LABEL: fcvtx_f32_f64:
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; CHECK: fcvtx z0.s, p0/m, z1.d
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtx.f32f64(<vscale x 4 x float> %a,
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<vscale x 2 x i1> %pg,
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<vscale x 2 x double> %b)
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ret <vscale x 4 x float> %out
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}
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;
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; FCVTXNT
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;
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define <vscale x 4 x float> @fcvtxnt_f32_f64(<vscale x 4 x float> %a, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b) {
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; CHECK-LABEL: fcvtxnt_f32_f64:
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; CHECK: fcvtxnt z0.s, p0/m, z1.d
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtxnt.f32f64(<vscale x 4 x float> %a,
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<vscale x 2 x i1> %pg,
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<vscale x 2 x double> %b)
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ret <vscale x 4 x float> %out
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}
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declare <vscale x 4 x float> @llvm.aarch64.sve.fcvtlt.f32f16(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 8 x half>)
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declare <vscale x 2 x double> @llvm.aarch64.sve.fcvtlt.f64f32(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 4 x float>)
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declare <vscale x 8 x half> @llvm.aarch64.sve.fcvtnt.f16f32(<vscale x 8 x half>, <vscale x 4 x i1>, <vscale x 4 x float>)
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declare <vscale x 4 x float> @llvm.aarch64.sve.fcvtnt.f32f64(<vscale x 4 x float>, <vscale x 2 x i1>, <vscale x 2 x double>)
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declare <vscale x 4 x float> @llvm.aarch64.sve.fcvtx.f32f64(<vscale x 4 x float>, <vscale x 2 x i1>, <vscale x 2 x double>)
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declare <vscale x 4 x float> @llvm.aarch64.sve.fcvtxnt.f32f64(<vscale x 4 x float>, <vscale x 2 x i1>, <vscale x 2 x double>)
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