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https://github.com/RPCS3/llvm-mirror.git
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b7041a91bb
Summary: Implements the following intrinsics: - @llvm.aarch64.sve.dup - @llvm.aarch64.sve.mul.lane - @llvm.aarch64.sve.mla.lane - @llvm.aarch64.sve.mls.lane Reviewers: c-rhodes, sdesmalen, dancgr, efriedma, rengolin Reviewed By: sdesmalen Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74222
120 lines
5.8 KiB
LLVM
120 lines
5.8 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
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;
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; MUL
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;
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define <vscale x 2 x i64> @mul_lane_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: mul_lane_d:
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; CHECK: mul z0.d, z0.d, z1.d[1]
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.mul.lane.nxv2i64(<vscale x 2 x i64> %a,
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<vscale x 2 x i64> %b,
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i32 1)
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ret <vscale x 2 x i64> %out
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}
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define <vscale x 4 x i32> @mul_lane_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: mul_lane_s:
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; CHECK: mul z0.s, z0.s, z1.s[1]
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.lane.nxv4i32(<vscale x 4 x i32> %a,
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<vscale x 4 x i32> %b,
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i32 1)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 8 x i16> @mul_lane_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: mul_lane_h:
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; CHECK: mul z0.h, z0.h, z1.h[1]
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.mul.lane.nxv8i16(<vscale x 8 x i16> %a,
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<vscale x 8 x i16> %b,
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i32 1)
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ret <vscale x 8 x i16> %out
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}
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;
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; MLA
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;
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define <vscale x 2 x i64> @mla_lane_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
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; CHECK-LABEL: mla_lane_d:
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; CHECK: mla z0.d, z1.d, z2.d[1]
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.mla.lane.nxv2i64(<vscale x 2 x i64> %a,
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<vscale x 2 x i64> %b,
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<vscale x 2 x i64> %c,
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i32 1)
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ret <vscale x 2 x i64> %out
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}
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define <vscale x 4 x i32> @mla_lane_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
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; CHECK-LABEL: mla_lane_s:
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; CHECK: mla z0.s, z1.s, z2.s[1]
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.lane.nxv4i32(<vscale x 4 x i32> %a,
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<vscale x 4 x i32> %b,
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<vscale x 4 x i32> %c,
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i32 1)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 8 x i16> @mla_lane_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
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; CHECK-LABEL: mla_lane_h:
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; CHECK: mla z0.h, z1.h, z2.h[1]
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.mla.lane.nxv8i16(<vscale x 8 x i16> %a,
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<vscale x 8 x i16> %b,
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<vscale x 8 x i16> %c,
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i32 1)
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ret <vscale x 8 x i16> %out
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}
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;
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; MLS
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;
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define <vscale x 2 x i64> @mls_lane_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
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; CHECK-LABEL: mls_lane_d:
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; CHECK: mls z0.d, z1.d, z2.d[1]
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.mls.lane.nxv2i64(<vscale x 2 x i64> %a,
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<vscale x 2 x i64> %b,
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<vscale x 2 x i64> %c,
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i32 1)
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ret <vscale x 2 x i64> %out
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}
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define <vscale x 4 x i32> @mls_lane_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
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; CHECK-LABEL: mls_lane_s:
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; CHECK: mls z0.s, z1.s, z2.s[1]
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.mls.lane.nxv4i32(<vscale x 4 x i32> %a,
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<vscale x 4 x i32> %b,
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<vscale x 4 x i32> %c,
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i32 1)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 8 x i16> @mls_lane_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
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; CHECK-LABEL: mls_lane_h:
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; CHECK: mls z0.h, z1.h, z2.h[1]
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.mls.lane.nxv8i16(<vscale x 8 x i16> %a,
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<vscale x 8 x i16> %b,
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<vscale x 8 x i16> %c,
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i32 1)
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ret <vscale x 8 x i16> %out
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}
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declare <vscale x 8 x i16> @llvm.aarch64.sve.mul.lane.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.mul.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.mul.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.mla.lane.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.mla.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.mla.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i32)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.mls.lane.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.mls.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.mls.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i32)
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