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402abf7a14
fadd/fmul reductions without reassoc are lowered to VECREDUCE_STRICT_FADD/FMUL nodes, which don't have legalization support. Until that is in place, expand these intrinsics on ARM and AArch64. Other targets always expand the vector reduction intrinsics. Additionally expand fmax/fmin reductions without nonan flag on AArch64, as the backend asserts that the flag is present when lowering VECREDUCE_FMIN/FMAX. This fixes https://bugs.llvm.org/show_bug.cgi?id=44600. Differential Revision: https://reviews.llvm.org/D73135
89 lines
3.2 KiB
LLVM
89 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
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declare half @llvm.experimental.vector.reduce.fmax.v1f16(<1 x half> %a)
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declare float @llvm.experimental.vector.reduce.fmax.v1f32(<1 x float> %a)
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declare double @llvm.experimental.vector.reduce.fmax.v1f64(<1 x double> %a)
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declare fp128 @llvm.experimental.vector.reduce.fmax.v1f128(<1 x fp128> %a)
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declare float @llvm.experimental.vector.reduce.fmax.v3f32(<3 x float> %a)
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declare fp128 @llvm.experimental.vector.reduce.fmax.v2f128(<2 x fp128> %a)
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declare float @llvm.experimental.vector.reduce.fmax.v16f32(<16 x float> %a)
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define half @test_v1f16(<1 x half> %a) nounwind {
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; CHECK-LABEL: test_v1f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call half @llvm.experimental.vector.reduce.fmax.v1f16(<1 x half> %a)
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ret half %b
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}
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define float @test_v1f32(<1 x float> %a) nounwind {
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; CHECK-LABEL: test_v1f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
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; CHECK-NEXT: ret
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%b = call float @llvm.experimental.vector.reduce.fmax.v1f32(<1 x float> %a)
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ret float %b
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}
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define double @test_v1f64(<1 x double> %a) nounwind {
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; CHECK-LABEL: test_v1f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call double @llvm.experimental.vector.reduce.fmax.v1f64(<1 x double> %a)
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ret double %b
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}
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define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
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; CHECK-LABEL: test_v1f128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call fp128 @llvm.experimental.vector.reduce.fmax.v1f128(<1 x fp128> %a)
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ret fp128 %b
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}
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; TODO: This doesn't work, because ExpandReductions only supports power of two
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; unordered reductions.
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;define float @test_v3f32(<3 x float> %a) nounwind {
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; %b = call float @llvm.experimental.vector.reduce.fmax.v3f32(<3 x float> %a)
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; ret float %b
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;}
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define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
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; CHECK-LABEL: test_v2f128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #48 // =48
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; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
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; CHECK-NEXT: stp q0, q1, [sp] // 32-byte Folded Spill
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; CHECK-NEXT: bl __gttf2
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; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
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; CHECK-NEXT: cmp w0, #0 // =0
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; CHECK-NEXT: b.le .LBB4_2
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; CHECK-NEXT: // %bb.1:
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; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
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; CHECK-NEXT: .LBB4_2:
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; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
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; CHECK-NEXT: add sp, sp, #48 // =48
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; CHECK-NEXT: ret
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%b = call fp128 @llvm.experimental.vector.reduce.fmax.v2f128(<2 x fp128> %a)
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ret fp128 %b
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}
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define float @test_v16f32(<16 x float> %a) nounwind {
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; CHECK-LABEL: test_v16f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmaxnm v1.4s, v1.4s, v3.4s
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; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: dup v1.4s, v0.s[1]
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; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
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; CHECK-NEXT: ret
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%b = call float @llvm.experimental.vector.reduce.fmax.v16f32(<16 x float> %a)
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ret float %b
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}
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