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f48eb88663
Under MVE, we do not have any lowering for fminimum, which a vector_reduce_fmin without NoNan will be expanded into. As with the other recent patches, force this to expand in the pre-isel pass. Note that Neon lowering would be OK because the scalar fminimum uses the vector VMIN instruction, but is probably better to just rely on the scalar operations, which is what is done here. Also fixes what appears to be the reversal of INF vs -INF in the vector_reduce_fmin widening code.
78 lines
2.6 KiB
LLVM
78 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
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declare half @llvm.experimental.vector.reduce.fmax.v1f16(<1 x half> %a)
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declare float @llvm.experimental.vector.reduce.fmax.v1f32(<1 x float> %a)
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declare double @llvm.experimental.vector.reduce.fmax.v1f64(<1 x double> %a)
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declare fp128 @llvm.experimental.vector.reduce.fmax.v1f128(<1 x fp128> %a)
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declare float @llvm.experimental.vector.reduce.fmax.v3f32(<3 x float> %a)
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declare fp128 @llvm.experimental.vector.reduce.fmax.v2f128(<2 x fp128> %a)
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declare float @llvm.experimental.vector.reduce.fmax.v16f32(<16 x float> %a)
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define half @test_v1f16(<1 x half> %a) nounwind {
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; CHECK-LABEL: test_v1f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call nnan half @llvm.experimental.vector.reduce.fmax.v1f16(<1 x half> %a)
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ret half %b
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}
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define float @test_v1f32(<1 x float> %a) nounwind {
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; CHECK-LABEL: test_v1f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
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; CHECK-NEXT: ret
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%b = call nnan float @llvm.experimental.vector.reduce.fmax.v1f32(<1 x float> %a)
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ret float %b
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}
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define double @test_v1f64(<1 x double> %a) nounwind {
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; CHECK-LABEL: test_v1f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call nnan double @llvm.experimental.vector.reduce.fmax.v1f64(<1 x double> %a)
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ret double %b
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}
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define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
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; CHECK-LABEL: test_v1f128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call nnan fp128 @llvm.experimental.vector.reduce.fmax.v1f128(<1 x fp128> %a)
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ret fp128 %b
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}
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define float @test_v3f32(<3 x float> %a) nounwind {
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; CHECK-LABEL: test_v3f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-8388608
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; CHECK-NEXT: fmov s1, w8
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; CHECK-NEXT: mov v0.s[3], v1.s[0]
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; CHECK-NEXT: fmaxnmv s0, v0.4s
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; CHECK-NEXT: ret
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%b = call nnan float @llvm.experimental.vector.reduce.fmax.v3f32(<3 x float> %a)
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ret float %b
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}
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define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
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; CHECK-LABEL: test_v2f128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: b fmaxl
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%b = call nnan fp128 @llvm.experimental.vector.reduce.fmax.v2f128(<2 x fp128> %a)
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ret fp128 %b
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}
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define float @test_v16f32(<16 x float> %a) nounwind {
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; CHECK-LABEL: test_v16f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmaxnm v1.4s, v1.4s, v3.4s
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; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: fmaxnmv s0, v0.4s
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; CHECK-NEXT: ret
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%b = call nnan float @llvm.experimental.vector.reduce.fmax.v16f32(<16 x float> %a)
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ret float %b
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}
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