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https://github.com/RPCS3/llvm-mirror.git
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5f91239343
This patch uses the mechanism from D62995 to strengthen the definitions of the reduction intrinsics by letting the scalar result/accumulator type be overloaded from the vector element type. For example: ; The LLVM LangRef specifies that the scalar result must equal the ; vector element type, but this is not checked/enforced by LLVM. declare i32 @llvm.experimental.vector.reduce.or.i32.v4i32(<4 x i32> %a) This patch changes that into: declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> %a) Which has the type-constraint more explicit and causes LLVM to check the result type with the vector element type. Reviewers: RKSimon, arsenm, rnk, greened, aemerson Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D62996 llvm-svn: 363240
178 lines
5.6 KiB
LLVM
178 lines
5.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
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declare i1 @llvm.experimental.vector.reduce.umax.v1i1(<1 x i1> %a)
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declare i8 @llvm.experimental.vector.reduce.umax.v1i8(<1 x i8> %a)
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declare i16 @llvm.experimental.vector.reduce.umax.v1i16(<1 x i16> %a)
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declare i24 @llvm.experimental.vector.reduce.umax.v1i24(<1 x i24> %a)
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declare i32 @llvm.experimental.vector.reduce.umax.v1i32(<1 x i32> %a)
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declare i64 @llvm.experimental.vector.reduce.umax.v1i64(<1 x i64> %a)
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declare i128 @llvm.experimental.vector.reduce.umax.v1i128(<1 x i128> %a)
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declare i8 @llvm.experimental.vector.reduce.umax.v3i8(<3 x i8> %a)
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declare i8 @llvm.experimental.vector.reduce.umax.v9i8(<9 x i8> %a)
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declare i32 @llvm.experimental.vector.reduce.umax.v3i32(<3 x i32> %a)
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declare i1 @llvm.experimental.vector.reduce.umax.v4i1(<4 x i1> %a)
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declare i24 @llvm.experimental.vector.reduce.umax.v4i24(<4 x i24> %a)
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declare i128 @llvm.experimental.vector.reduce.umax.v2i128(<2 x i128> %a)
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declare i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32> %a)
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define i1 @test_v1i1(<1 x i1> %a) nounwind {
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; CHECK-LABEL: test_v1i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w0, w0, #0x1
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; CHECK-NEXT: ret
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%b = call i1 @llvm.experimental.vector.reduce.umax.v1i1(<1 x i1> %a)
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ret i1 %b
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}
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define i8 @test_v1i8(<1 x i8> %a) nounwind {
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; CHECK-LABEL: test_v1i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: umov w0, v0.b[0]
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; CHECK-NEXT: ret
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%b = call i8 @llvm.experimental.vector.reduce.umax.v1i8(<1 x i8> %a)
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ret i8 %b
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}
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define i16 @test_v1i16(<1 x i16> %a) nounwind {
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; CHECK-LABEL: test_v1i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: umov w0, v0.h[0]
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; CHECK-NEXT: ret
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%b = call i16 @llvm.experimental.vector.reduce.umax.v1i16(<1 x i16> %a)
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ret i16 %b
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}
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define i24 @test_v1i24(<1 x i24> %a) nounwind {
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; CHECK-LABEL: test_v1i24:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call i24 @llvm.experimental.vector.reduce.umax.v1i24(<1 x i24> %a)
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ret i24 %b
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}
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define i32 @test_v1i32(<1 x i32> %a) nounwind {
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; CHECK-LABEL: test_v1i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%b = call i32 @llvm.experimental.vector.reduce.umax.v1i32(<1 x i32> %a)
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ret i32 %b
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}
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define i64 @test_v1i64(<1 x i64> %a) nounwind {
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; CHECK-LABEL: test_v1i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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%b = call i64 @llvm.experimental.vector.reduce.umax.v1i64(<1 x i64> %a)
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ret i64 %b
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}
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define i128 @test_v1i128(<1 x i128> %a) nounwind {
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; CHECK-LABEL: test_v1i128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call i128 @llvm.experimental.vector.reduce.umax.v1i128(<1 x i128> %a)
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ret i128 %b
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}
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define i8 @test_v3i8(<3 x i8> %a) nounwind {
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; CHECK-LABEL: test_v3i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi d0, #0000000000000000
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; CHECK-NEXT: mov v0.h[0], w0
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; CHECK-NEXT: mov v0.h[1], w1
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; CHECK-NEXT: mov v0.h[2], w2
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; CHECK-NEXT: bic v0.4h, #255, lsl #8
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; CHECK-NEXT: umaxv h0, v0.4h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%b = call i8 @llvm.experimental.vector.reduce.umax.v3i8(<3 x i8> %a)
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ret i8 %b
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}
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define i8 @test_v9i8(<9 x i8> %a) nounwind {
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; CHECK-LABEL: test_v9i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov v0.b[9], wzr
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; CHECK-NEXT: mov v0.b[10], wzr
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; CHECK-NEXT: mov v0.b[11], wzr
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; CHECK-NEXT: mov v0.b[12], wzr
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; CHECK-NEXT: mov v0.b[13], wzr
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; CHECK-NEXT: mov v0.b[14], wzr
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; CHECK-NEXT: mov v0.b[15], wzr
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; CHECK-NEXT: umaxv b0, v0.16b
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%b = call i8 @llvm.experimental.vector.reduce.umax.v9i8(<9 x i8> %a)
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ret i8 %b
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}
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define i32 @test_v3i32(<3 x i32> %a) nounwind {
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; CHECK-LABEL: test_v3i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov v0.s[3], wzr
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; CHECK-NEXT: umaxv s0, v0.4s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%b = call i32 @llvm.experimental.vector.reduce.umax.v3i32(<3 x i32> %a)
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ret i32 %b
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}
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define i1 @test_v4i1(<4 x i1> %a) nounwind {
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; CHECK-LABEL: test_v4i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4h, #1
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; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: umaxv h0, v0.4h
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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%b = call i1 @llvm.experimental.vector.reduce.umax.v4i1(<4 x i1> %a)
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ret i1 %b
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}
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define i24 @test_v4i24(<4 x i24> %a) nounwind {
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; CHECK-LABEL: test_v4i24:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bic v0.4s, #255, lsl #24
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; CHECK-NEXT: umaxv s0, v0.4s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%b = call i24 @llvm.experimental.vector.reduce.umax.v4i24(<4 x i24> %a)
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ret i24 %b
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}
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define i128 @test_v2i128(<2 x i128> %a) nounwind {
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; CHECK-LABEL: test_v2i128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, x2
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; CHECK-NEXT: csel x8, x0, x2, hi
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; CHECK-NEXT: cmp x1, x3
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; CHECK-NEXT: csel x9, x0, x2, hi
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; CHECK-NEXT: csel x0, x8, x9, eq
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; CHECK-NEXT: csel x1, x1, x3, hi
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; CHECK-NEXT: ret
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%b = call i128 @llvm.experimental.vector.reduce.umax.v2i128(<2 x i128> %a)
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ret i128 %b
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}
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define i32 @test_v16i32(<16 x i32> %a) nounwind {
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; CHECK-LABEL: test_v16i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umax v1.4s, v1.4s, v3.4s
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; CHECK-NEXT: umax v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: umaxv s0, v0.4s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%b = call i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32> %a)
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ret i32 %b
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}
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