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78a5d52036
Summary: - `dead-mi-elimination` assumes MIR in the SSA form and cannot be arranged after phi elimination or DeSSA. It's enhanced to handle the dead register definition by skipping use check on it. Once a register def is `dead`, all its uses, if any, should be `undef`. - Re-arrange the DIE in RA phase for AMDGPU by placing it directly after `detect-dead-lanes`. - Many relevant tests are refined due to different register assignment. Reviewers: rampitec, qcolombet, sunfish Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72709
29 lines
780 B
LLVM
29 lines
780 B
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs %s -o - | FileCheck %s
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; CHECK-LABEL: foo
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; CHECK-NOT: BUFFER_LOAD_DWORDX2_OFFSET
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; After dead code elimination, that buffer load should be eliminated finally
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; after dead lane detection.
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define amdgpu_kernel void @foo() {
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entry:
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switch i8 undef, label %foo.exit [
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i8 4, label %sw.bb4
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i8 10, label %sw.bb10
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]
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sw.bb4:
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%x = load i64, i64 addrspace(1)* undef, align 8
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%c = sitofp i64 %x to float
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%v = insertelement <2 x float> <float undef, float 0.000000e+00>, float %c, i32 0
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br label %foo.exit
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sw.bb10:
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unreachable
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foo.exit:
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%agg = phi <2 x float> [ %v, %sw.bb4 ], [ zeroinitializer, %entry ]
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%s = extractelement <2 x float> %agg, i32 1
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store float %s, float addrspace(1)* undef, align 4
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ret void
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}
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