mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-31 20:51:52 +01:00
a70016c8d5
Add the scratch wave offset to the scratch buffer descriptor (SRSrc) in the entry function prologue. This allows us to removes the scratch wave offset register from the calling convention ABI. As part of this change, allow the use of an inline constant zero for the SOffset of MUBUF instructions accessing the stack in entry functions when a frame pointer is not requested/required. Entry functions with calls still need to set up the calling convention ABI stack pointer register, and reference it in order to address arguments of called functions. The ABI stack pointer register remains unswizzled, but is now wave-relative instead of queue-relative. Non-entry functions also use an inline constant zero SOffset for wave-relative scratch access, but continue to use the stack and frame pointers as before. When the stack or frame pointer is converted to a swizzled offset it is now scaled directly, as the scratch wave offset no longer needs to be subtracted first. Update llvm/docs/AMDGPUUsage.rst to reflect these changes to the calling convention. Tags: #llvm Differential Revision: https://reviews.llvm.org/D75138
36 lines
1.4 KiB
LLVM
36 lines
1.4 KiB
LLVM
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
|
|
|
|
; FIXME: Requires stack object to not assert
|
|
; GCN-LABEL: {{^}}test_ps:
|
|
; GCN: s_load_dwordx2 s[4:5], s[0:1], 0x0
|
|
; GCN: buffer_store_dword v0, off, s[4:7], 0 offset:4
|
|
; GCN: s_load_dword s{{[0-9]+}}, s[0:1], 0x0
|
|
; GCN-NEXT: s_waitcnt
|
|
; GCN-NEXT: ; return
|
|
define amdgpu_ps i32 @test_ps() #1 {
|
|
%alloca = alloca i32, addrspace(5)
|
|
store volatile i32 0, i32 addrspace(5)* %alloca
|
|
%implicit_buffer_ptr = call i8 addrspace(4)* @llvm.amdgcn.implicit.buffer.ptr()
|
|
%buffer_ptr = bitcast i8 addrspace(4)* %implicit_buffer_ptr to i32 addrspace(4)*
|
|
%value = load volatile i32, i32 addrspace(4)* %buffer_ptr
|
|
ret i32 %value
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}test_cs:
|
|
; GCN: s_mov_b64 s[4:5], s[0:1]
|
|
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[4:7], 0 offset:4
|
|
; GCN: s_load_dword s0, s[0:1], 0x0
|
|
define amdgpu_cs i32 @test_cs() #1 {
|
|
%alloca = alloca i32, addrspace(5)
|
|
store volatile i32 0, i32 addrspace(5)* %alloca
|
|
%implicit_buffer_ptr = call i8 addrspace(4)* @llvm.amdgcn.implicit.buffer.ptr()
|
|
%buffer_ptr = bitcast i8 addrspace(4)* %implicit_buffer_ptr to i32 addrspace(4)*
|
|
%value = load volatile i32, i32 addrspace(4)* %buffer_ptr
|
|
ret i32 %value
|
|
}
|
|
|
|
declare i8 addrspace(4)* @llvm.amdgcn.implicit.buffer.ptr() #0
|
|
|
|
attributes #0 = { nounwind readnone speculatable }
|
|
attributes #1 = { nounwind }
|