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llvm-mirror/test/CodeGen/Hexagon/atomic-store-byte.ll
Brendon Cahoon 4b5fd94277 Align store conditional address
In cases where the alignment of the datatype is smaller than
expected by the instruction, the address is aligned. The aligned
address is used for the load, but wasn't used for the store
conditional, which resulted in a run-time alignment exception.
2020-07-30 10:42:00 -05:00

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LLVM

; RUN: llc -mtriple=hexagon < %s | FileCheck %s
; Test that the address for a store conditional for a byte is aligned
; correctly to use the memw_locked instruction.
; CHECK: [[REG:(r[0-9]+)]] = and(r{{[0-9]+}},#-4)
; CHECK: = memw_locked([[REG]])
; CHECK: memw_locked([[REG]],p{{[0-4]}}) =
@foo.a00 = internal global i8 0, align 1
; Function Attrs: nofree norecurse nounwind
define dso_local void @foo() local_unnamed_addr #0 {
entry:
%0 = cmpxchg volatile i8* @foo.a00, i8 0, i8 1 seq_cst seq_cst
ret void
}