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f9eef6e26a
This affects the following instructions: Tag: M4_mpyrr_addr Syntax: Ry32 = add(Ru32,mpyi(Ry32,Rs32)) Tag: M4_mpyri_addr_u2 Syntax: Rd32 = add(Ru32,mpyi(#u6:2,Rs32)) Tag: M4_mpyri_addr Syntax: Rd32 = add(Ru32,mpyi(Rs32,#u6)) Tag: M4_mpyri_addi Syntax: Rd32 = add(#u6,mpyi(Rs32,#U6)) Tag: M4_mpyrr_addi Syntax: Rd32 = add(#u6,mpyi(Rs32,Rt32)) Tag: S4_addaddi Syntax: Rd32 = add(Rs32,add(Ru32,#s6)) Tag: S4_subaddi Syntax: Rd32 = add(Rs32,sub(#s6,Ru32)) Tag: S4_or_andix Syntax: Rx32 = or(Ru32,and(Rx32,#s10)) Tag: S4_andi_asl_ri Syntax: Rx32 = and(#u8,asl(Rx32,#U5)) Tag: S4_ori_asl_ri Syntax: Rx32 = or(#u8,asl(Rx32,#U5)) Tag: S4_addi_asl_ri Syntax: Rx32 = add(#u8,asl(Rx32,#U5)) Tag: S4_subi_asl_ri Syntax: Rx32 = sub(#u8,asl(Rx32,#U5)) Tag: S4_andi_lsr_ri Syntax: Rx32 = and(#u8,lsr(Rx32,#U5)) Tag: S4_ori_lsr_ri Syntax: Rx32 = or(#u8,lsr(Rx32,#U5)) Tag: S4_addi_lsr_ri Syntax: Rx32 = add(#u8,lsr(Rx32,#U5)) Tag: S4_subi_lsr_ri Syntax: Rx32 = sub(#u8,lsr(Rx32,#U5))
22 lines
579 B
LLVM
22 lines
579 B
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK-LABEL: t0
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; CHECK: r0 = add(r1,add(r0,#23))
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define i32 @t0(i32 %a0, i32 %a1) #0 {
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%v0 = add i32 %a1, 23
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%v1 = add i32 %a0, %v0
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ret i32 %v1
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}
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; CHECK-LABEL: t1
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; CHECK: r[[R:[0-9]+]] = add(r1,r0)
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; CHECK: r0 = add(r[[R]],#23)
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define i32 @t1(i32 %a0, i32 %a1) #1 {
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%v0 = add i32 %a1, 23
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%v1 = add i32 %a0, %v0
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ret i32 %v1
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}
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attributes #0 = { nounwind readnone "target-cpu"="hexagonv62" "target-features"="+compound" }
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attributes #1 = { nounwind readnone "target-cpu"="hexagonv62" "target-features"="-compound" }
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