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26f603eb22
This patch adds MXCSR as a reserved physical register and models its use by X86 SSE instructions. It also adds flag "mayRaiseFPException" for the instructions that possibly can raise FP exception according to the architecture definition. Following what SystemZ and other targets does, only the current rounding modes and the IEEE exception masks are modeled. *Changes* of the MXCSR due to exceptions are not modeled. Patch by Pengfei Wang Differential Revision: https://reviews.llvm.org/D68121
37 lines
1.5 KiB
YAML
37 lines
1.5 KiB
YAML
# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
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# This test ensures that the MIR parser parses the fast math instruction flags.
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...
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---
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name: baz
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body: |
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bb.0.entry:
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liveins: $xmm0
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; CHECK: %0:fr32 = COPY $xmm0
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%0:fr32 = COPY $xmm0
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; CHECK: %1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
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%1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
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; CHECK: %2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
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%2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
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; CHECK: %3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
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%3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
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; CHECK: %4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
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%4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
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; CHECK: %5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
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%5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
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; CHECK: %6:fr32 = afn VMULSSrr %5, %5, implicit $mxcsr
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%6:fr32 = afn VMULSSrr %5, %5, implicit $mxcsr
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; CHECK: %7:fr32 = reassoc VMULSSrr %6, %6, implicit $mxcsr
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%7:fr32 = reassoc VMULSSrr %6, %6, implicit $mxcsr
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; CHECK: %8:fr32 = nsz arcp contract afn reassoc VMULSSrr %7, %7, implicit $mxcsr
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%8:fr32 = nsz arcp contract afn reassoc VMULSSrr %7, %7, implicit $mxcsr
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; CHECK: %9:fr32 = contract afn reassoc VMULSSrr %8, %8, implicit $mxcsr
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%9:fr32 = contract afn reassoc VMULSSrr %8, %8, implicit $mxcsr
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; CHECK: $xmm0 = COPY %9
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$xmm0 = COPY %9
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; CHECK: RET 0, $xmm0
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RET 0, $xmm0
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...
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