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llvm-mirror/test/CodeGen/MIR/X86/fastmath.mir
Craig Topper 26f603eb22 [X86] Model MXCSR for all SSE instructions
This patch adds MXCSR as a reserved physical register and models its use
by X86 SSE instructions. It also adds flag "mayRaiseFPException" for the
instructions that possibly can raise FP exception according to the
architecture definition.

Following what SystemZ and other targets does, only the current rounding
modes and the IEEE exception masks are modeled. *Changes* of the MXCSR
due to exceptions are not modeled.

Patch by Pengfei Wang

Differential Revision: https://reviews.llvm.org/D68121
2019-10-30 15:07:49 -07:00

37 lines
1.5 KiB
YAML

# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the fast math instruction flags.
...
---
name: baz
body: |
bb.0.entry:
liveins: $xmm0
; CHECK: %0:fr32 = COPY $xmm0
%0:fr32 = COPY $xmm0
; CHECK: %1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
%1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
; CHECK: %2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
%2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
; CHECK: %3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
%3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
; CHECK: %4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
%4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
; CHECK: %5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
%5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
; CHECK: %6:fr32 = afn VMULSSrr %5, %5, implicit $mxcsr
%6:fr32 = afn VMULSSrr %5, %5, implicit $mxcsr
; CHECK: %7:fr32 = reassoc VMULSSrr %6, %6, implicit $mxcsr
%7:fr32 = reassoc VMULSSrr %6, %6, implicit $mxcsr
; CHECK: %8:fr32 = nsz arcp contract afn reassoc VMULSSrr %7, %7, implicit $mxcsr
%8:fr32 = nsz arcp contract afn reassoc VMULSSrr %7, %7, implicit $mxcsr
; CHECK: %9:fr32 = contract afn reassoc VMULSSrr %8, %8, implicit $mxcsr
%9:fr32 = contract afn reassoc VMULSSrr %8, %8, implicit $mxcsr
; CHECK: $xmm0 = COPY %9
$xmm0 = COPY %9
; CHECK: RET 0, $xmm0
RET 0, $xmm0
...