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c0439216a4
This adds the required extension to RISC-V's getRegForInlineAsmConstraint in order to be able to correctly distringuish between the 32 and 64-bit floating point registers when the generic fX name appears in inlineasm clobber contraints. It also adds a check to validate that callee saved floating point registers are only saved in this case when a hard-float ABI is selected. Differential Revision: https://reviews.llvm.org/D64751 llvm-svn: 367397
62 lines
2.3 KiB
LLVM
62 lines
2.3 KiB
LLVM
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IF %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IF %s
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; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32ID %s
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; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64ID %s
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define void @testcase() nounwind {
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; RV32I-LABEL: testcase:
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; RV32I: sw s1, {{[0-9]+}}(sp)
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; RV32I-NEXT: sw s2, {{[0-9]+}}(sp)
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; RV32I-NOT: fsw fs0, {{[0-9]+}}(sp)
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; RV32I-NOT: fsd fs0, {{[0-9]+}}(sp)
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;
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; RV64I-LABEL: testcase:
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; RV64I: sd s1, {{[0-9]+}}(sp)
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; RV64I-NEXT: sd s2, {{[0-9]+}}(sp)
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; RV64I-NOT: fsw fs0, {{[0-9]+}}(sp)
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; RV64I-NOT: fsd fs0, {{[0-9]+}}(sp)
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;
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; RV32IF-LABEL: testcase:
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; RV32IF: sw s1, {{[0-9]+}}(sp)
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; RV32IF-NEXT: sw s2, {{[0-9]+}}(sp)
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; RV32IF-NEXT: fsw fs0, {{[0-9]+}}(sp)
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; RV32IF-NEXT: fsw fs1, {{[0-9]+}}(sp)
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;
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; RV64IF-LABEL: testcase:
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; RV64IF: sd s1, {{[0-9]+}}(sp)
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; RV64IF-NEXT: sd s2, {{[0-9]+}}(sp)
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; RV64IF-NEXT: fsw fs0, {{[0-9]+}}(sp)
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; RV64IF-NEXT: fsw fs1, {{[0-9]+}}(sp)
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;
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; RV32ID-LABEL: testcase:
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; RV32ID: sw s1, {{[0-9]+}}(sp)
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; RV32ID-NEXT: sw s2, {{[0-9]+}}(sp)
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; RV32ID-NEXT: fsd fs0, {{[0-9]+}}(sp)
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; RV32ID-NEXT: fsd fs1, {{[0-9]+}}(sp)
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;
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; RV64ID-LABEL: testcase:
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; RV64ID: sd s1, {{[0-9]+}}(sp)
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; RV64ID-NEXT: sd s2, {{[0-9]+}}(sp)
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; RV64ID-NEXT: fsd fs0, {{[0-9]+}}(sp)
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; RV64ID-NEXT: fsd fs1, {{[0-9]+}}(sp)
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tail call void asm sideeffect "", "~{f8},~{f9},~{x9},~{x18}"()
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ret void
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}
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