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https://github.com/RPCS3/llvm-mirror.git
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1ae2a5de8f
We would like to split the SP adjustment to reduce the instructions in
prologue and epilogue as the following case. In this way, the offset of
the callee saved register could fit in a single store.
add sp,sp,-2032
sw ra,2028(sp)
sw s0,2024(sp)
sw s1,2020(sp)
sw s3,2012(sp)
sw s4,2008(sp)
add sp,sp,-64
Differential Revision: https://reviews.llvm.org/D68011
llvm-svn: 373688
542 lines
15 KiB
LLVM
542 lines
15 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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declare void @callee(i8*)
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define void @caller32() nounwind {
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; RV32I-LABEL: caller32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -64
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; RV32I-NEXT: sw ra, 60(sp)
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; RV32I-NEXT: sw s0, 56(sp)
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; RV32I-NEXT: addi s0, sp, 64
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; RV32I-NEXT: andi sp, sp, -32
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; RV32I-NEXT: addi a0, sp, 32
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; RV32I-NEXT: call callee
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; RV32I-NEXT: addi sp, s0, -64
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; RV32I-NEXT: lw s0, 56(sp)
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; RV32I-NEXT: lw ra, 60(sp)
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; RV32I-NEXT: addi sp, sp, 64
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: caller32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -64
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; RV64I-NEXT: sd ra, 56(sp)
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; RV64I-NEXT: sd s0, 48(sp)
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; RV64I-NEXT: addi s0, sp, 64
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; RV64I-NEXT: andi sp, sp, -32
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; RV64I-NEXT: addi a0, sp, 32
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; RV64I-NEXT: call callee
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; RV64I-NEXT: addi sp, s0, -64
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; RV64I-NEXT: ld s0, 48(sp)
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; RV64I-NEXT: ld ra, 56(sp)
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; RV64I-NEXT: addi sp, sp, 64
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; RV64I-NEXT: ret
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%1 = alloca i8, align 32
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call void @callee(i8* %1)
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ret void
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}
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define void @caller_no_realign32() nounwind "no-realign-stack" {
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; RV32I-LABEL: caller_no_realign32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: mv a0, sp
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; RV32I-NEXT: call callee
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: caller_no_realign32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: mv a0, sp
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; RV64I-NEXT: call callee
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = alloca i8, align 32
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call void @callee(i8* %1)
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ret void
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}
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define void @caller64() nounwind {
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; RV32I-LABEL: caller64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -128
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; RV32I-NEXT: sw ra, 124(sp)
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; RV32I-NEXT: sw s0, 120(sp)
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; RV32I-NEXT: addi s0, sp, 128
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; RV32I-NEXT: andi sp, sp, -64
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; RV32I-NEXT: addi a0, sp, 64
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; RV32I-NEXT: call callee
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; RV32I-NEXT: addi sp, s0, -128
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; RV32I-NEXT: lw s0, 120(sp)
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; RV32I-NEXT: lw ra, 124(sp)
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; RV32I-NEXT: addi sp, sp, 128
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: caller64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -128
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; RV64I-NEXT: sd ra, 120(sp)
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; RV64I-NEXT: sd s0, 112(sp)
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; RV64I-NEXT: addi s0, sp, 128
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; RV64I-NEXT: andi sp, sp, -64
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; RV64I-NEXT: addi a0, sp, 64
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; RV64I-NEXT: call callee
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; RV64I-NEXT: addi sp, s0, -128
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; RV64I-NEXT: ld s0, 112(sp)
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; RV64I-NEXT: ld ra, 120(sp)
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; RV64I-NEXT: addi sp, sp, 128
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; RV64I-NEXT: ret
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%1 = alloca i8, align 64
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call void @callee(i8* %1)
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ret void
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}
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define void @caller_no_realign64() nounwind "no-realign-stack" {
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; RV32I-LABEL: caller_no_realign64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: mv a0, sp
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; RV32I-NEXT: call callee
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: caller_no_realign64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: mv a0, sp
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; RV64I-NEXT: call callee
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = alloca i8, align 64
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call void @callee(i8* %1)
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ret void
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}
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define void @caller128() nounwind {
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; RV32I-LABEL: caller128:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -256
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; RV32I-NEXT: sw ra, 252(sp)
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; RV32I-NEXT: sw s0, 248(sp)
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; RV32I-NEXT: addi s0, sp, 256
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; RV32I-NEXT: andi sp, sp, -128
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; RV32I-NEXT: addi a0, sp, 128
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; RV32I-NEXT: call callee
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; RV32I-NEXT: addi sp, s0, -256
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; RV32I-NEXT: lw s0, 248(sp)
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; RV32I-NEXT: lw ra, 252(sp)
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; RV32I-NEXT: addi sp, sp, 256
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: caller128:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -256
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; RV64I-NEXT: sd ra, 248(sp)
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; RV64I-NEXT: sd s0, 240(sp)
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; RV64I-NEXT: addi s0, sp, 256
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; RV64I-NEXT: andi sp, sp, -128
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; RV64I-NEXT: addi a0, sp, 128
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; RV64I-NEXT: call callee
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; RV64I-NEXT: addi sp, s0, -256
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; RV64I-NEXT: ld s0, 240(sp)
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; RV64I-NEXT: ld ra, 248(sp)
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; RV64I-NEXT: addi sp, sp, 256
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; RV64I-NEXT: ret
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%1 = alloca i8, align 128
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call void @callee(i8* %1)
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ret void
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}
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define void @caller_no_realign128() nounwind "no-realign-stack" {
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; RV32I-LABEL: caller_no_realign128:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: mv a0, sp
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; RV32I-NEXT: call callee
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: caller_no_realign128:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: mv a0, sp
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; RV64I-NEXT: call callee
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = alloca i8, align 128
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call void @callee(i8* %1)
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ret void
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}
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define void @caller256() nounwind {
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; RV32I-LABEL: caller256:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -512
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; RV32I-NEXT: sw ra, 508(sp)
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; RV32I-NEXT: sw s0, 504(sp)
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; RV32I-NEXT: addi s0, sp, 512
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; RV32I-NEXT: andi sp, sp, -256
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; RV32I-NEXT: addi a0, sp, 256
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; RV32I-NEXT: call callee
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; RV32I-NEXT: addi sp, s0, -512
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; RV32I-NEXT: lw s0, 504(sp)
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; RV32I-NEXT: lw ra, 508(sp)
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; RV32I-NEXT: addi sp, sp, 512
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: caller256:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -512
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; RV64I-NEXT: sd ra, 504(sp)
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; RV64I-NEXT: sd s0, 496(sp)
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; RV64I-NEXT: addi s0, sp, 512
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; RV64I-NEXT: andi sp, sp, -256
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; RV64I-NEXT: addi a0, sp, 256
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; RV64I-NEXT: call callee
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; RV64I-NEXT: addi sp, s0, -512
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; RV64I-NEXT: ld s0, 496(sp)
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; RV64I-NEXT: ld ra, 504(sp)
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; RV64I-NEXT: addi sp, sp, 512
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; RV64I-NEXT: ret
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%1 = alloca i8, align 256
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call void @callee(i8* %1)
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ret void
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}
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define void @caller_no_realign256() nounwind "no-realign-stack" {
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; RV32I-LABEL: caller_no_realign256:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: mv a0, sp
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; RV32I-NEXT: call callee
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: caller_no_realign256:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: mv a0, sp
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; RV64I-NEXT: call callee
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = alloca i8, align 256
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call void @callee(i8* %1)
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ret void
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}
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define void @caller512() nounwind {
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; RV32I-LABEL: caller512:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -1536
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; RV32I-NEXT: sw ra, 1532(sp)
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; RV32I-NEXT: sw s0, 1528(sp)
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; RV32I-NEXT: addi s0, sp, 1536
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; RV32I-NEXT: andi sp, sp, -512
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; RV32I-NEXT: addi a0, sp, 1024
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; RV32I-NEXT: call callee
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; RV32I-NEXT: addi sp, s0, -1536
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; RV32I-NEXT: lw s0, 1528(sp)
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; RV32I-NEXT: lw ra, 1532(sp)
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; RV32I-NEXT: addi sp, sp, 1536
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: caller512:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -1536
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; RV64I-NEXT: sd ra, 1528(sp)
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; RV64I-NEXT: sd s0, 1520(sp)
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; RV64I-NEXT: addi s0, sp, 1536
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; RV64I-NEXT: andi sp, sp, -512
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; RV64I-NEXT: addi a0, sp, 1024
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; RV64I-NEXT: call callee
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; RV64I-NEXT: addi sp, s0, -1536
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; RV64I-NEXT: ld s0, 1520(sp)
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; RV64I-NEXT: ld ra, 1528(sp)
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; RV64I-NEXT: addi sp, sp, 1536
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; RV64I-NEXT: ret
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%1 = alloca i8, align 512
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call void @callee(i8* %1)
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ret void
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}
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define void @caller_no_realign512() nounwind "no-realign-stack" {
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; RV32I-LABEL: caller_no_realign512:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: mv a0, sp
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; RV32I-NEXT: call callee
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: caller_no_realign512:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: mv a0, sp
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; RV64I-NEXT: call callee
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = alloca i8, align 512
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call void @callee(i8* %1)
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ret void
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}
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define void @caller1024() nounwind {
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; RV32I-LABEL: caller1024:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -2032
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; RV32I-NEXT: sw ra, 2028(sp)
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; RV32I-NEXT: sw s0, 2024(sp)
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; RV32I-NEXT: addi s0, sp, 2032
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; RV32I-NEXT: addi sp, sp, -1040
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; RV32I-NEXT: andi sp, sp, -1024
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; RV32I-NEXT: lui a0, 1
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; RV32I-NEXT: addi a0, a0, -2048
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; RV32I-NEXT: add a0, sp, a0
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; RV32I-NEXT: mv a0, a0
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; RV32I-NEXT: call callee
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; RV32I-NEXT: lui a0, 1
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; RV32I-NEXT: addi a0, a0, -1024
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; RV32I-NEXT: sub sp, s0, a0
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; RV32I-NEXT: addi sp, sp, 1040
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; RV32I-NEXT: lw s0, 2024(sp)
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; RV32I-NEXT: lw ra, 2028(sp)
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; RV32I-NEXT: addi sp, sp, 2032
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: caller1024:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -2032
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; RV64I-NEXT: sd ra, 2024(sp)
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; RV64I-NEXT: sd s0, 2016(sp)
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; RV64I-NEXT: addi s0, sp, 2032
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; RV64I-NEXT: addi sp, sp, -1040
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; RV64I-NEXT: andi sp, sp, -1024
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; RV64I-NEXT: lui a0, 1
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; RV64I-NEXT: addiw a0, a0, -2048
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; RV64I-NEXT: add a0, sp, a0
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; RV64I-NEXT: mv a0, a0
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; RV64I-NEXT: call callee
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; RV64I-NEXT: lui a0, 1
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; RV64I-NEXT: addiw a0, a0, -1024
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; RV64I-NEXT: sub sp, s0, a0
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; RV64I-NEXT: addi sp, sp, 1040
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; RV64I-NEXT: ld s0, 2016(sp)
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; RV64I-NEXT: ld ra, 2024(sp)
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; RV64I-NEXT: addi sp, sp, 2032
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; RV64I-NEXT: ret
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%1 = alloca i8, align 1024
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call void @callee(i8* %1)
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ret void
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}
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define void @caller_no_realign1024() nounwind "no-realign-stack" {
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; RV32I-LABEL: caller_no_realign1024:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: mv a0, sp
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; RV32I-NEXT: call callee
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: caller_no_realign1024:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: mv a0, sp
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; RV64I-NEXT: call callee
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = alloca i8, align 1024
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call void @callee(i8* %1)
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ret void
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}
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define void @caller2048() nounwind {
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; RV32I-LABEL: caller2048:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -2032
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; RV32I-NEXT: sw ra, 2028(sp)
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; RV32I-NEXT: sw s0, 2024(sp)
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; RV32I-NEXT: addi s0, sp, 2032
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; RV32I-NEXT: lui a0, 1
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; RV32I-NEXT: addi a0, a0, 16
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; RV32I-NEXT: sub sp, sp, a0
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; RV32I-NEXT: andi sp, sp, -2048
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; RV32I-NEXT: lui a0, 1
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; RV32I-NEXT: add a0, sp, a0
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; RV32I-NEXT: mv a0, a0
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; RV32I-NEXT: call callee
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; RV32I-NEXT: lui a0, 2
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; RV32I-NEXT: addi a0, a0, -2048
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; RV32I-NEXT: sub sp, s0, a0
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; RV32I-NEXT: lui a0, 1
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; RV32I-NEXT: addi a0, a0, 16
|
|
; RV32I-NEXT: add sp, sp, a0
|
|
; RV32I-NEXT: lw s0, 2024(sp)
|
|
; RV32I-NEXT: lw ra, 2028(sp)
|
|
; RV32I-NEXT: addi sp, sp, 2032
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: caller2048:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -2032
|
|
; RV64I-NEXT: sd ra, 2024(sp)
|
|
; RV64I-NEXT: sd s0, 2016(sp)
|
|
; RV64I-NEXT: addi s0, sp, 2032
|
|
; RV64I-NEXT: lui a0, 1
|
|
; RV64I-NEXT: addiw a0, a0, 16
|
|
; RV64I-NEXT: sub sp, sp, a0
|
|
; RV64I-NEXT: andi sp, sp, -2048
|
|
; RV64I-NEXT: lui a0, 1
|
|
; RV64I-NEXT: add a0, sp, a0
|
|
; RV64I-NEXT: mv a0, a0
|
|
; RV64I-NEXT: call callee
|
|
; RV64I-NEXT: lui a0, 2
|
|
; RV64I-NEXT: addiw a0, a0, -2048
|
|
; RV64I-NEXT: sub sp, s0, a0
|
|
; RV64I-NEXT: lui a0, 1
|
|
; RV64I-NEXT: addiw a0, a0, 16
|
|
; RV64I-NEXT: add sp, sp, a0
|
|
; RV64I-NEXT: ld s0, 2016(sp)
|
|
; RV64I-NEXT: ld ra, 2024(sp)
|
|
; RV64I-NEXT: addi sp, sp, 2032
|
|
; RV64I-NEXT: ret
|
|
%1 = alloca i8, align 2048
|
|
call void @callee(i8* %1)
|
|
ret void
|
|
}
|
|
|
|
define void @caller_no_realign2048() nounwind "no-realign-stack" {
|
|
; RV32I-LABEL: caller_no_realign2048:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: mv a0, sp
|
|
; RV32I-NEXT: call callee
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: caller_no_realign2048:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: mv a0, sp
|
|
; RV64I-NEXT: call callee
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
%1 = alloca i8, align 2048
|
|
call void @callee(i8* %1)
|
|
ret void
|
|
}
|
|
|
|
define void @caller4096() nounwind {
|
|
; RV32I-LABEL: caller4096:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -2032
|
|
; RV32I-NEXT: sw ra, 2028(sp)
|
|
; RV32I-NEXT: sw s0, 2024(sp)
|
|
; RV32I-NEXT: addi s0, sp, 2032
|
|
; RV32I-NEXT: lui a0, 3
|
|
; RV32I-NEXT: addi a0, a0, -2032
|
|
; RV32I-NEXT: sub sp, sp, a0
|
|
; RV32I-NEXT: srli a0, sp, 12
|
|
; RV32I-NEXT: slli sp, a0, 12
|
|
; RV32I-NEXT: lui a0, 2
|
|
; RV32I-NEXT: add a0, sp, a0
|
|
; RV32I-NEXT: mv a0, a0
|
|
; RV32I-NEXT: call callee
|
|
; RV32I-NEXT: lui a0, 3
|
|
; RV32I-NEXT: sub sp, s0, a0
|
|
; RV32I-NEXT: lui a0, 3
|
|
; RV32I-NEXT: addi a0, a0, -2032
|
|
; RV32I-NEXT: add sp, sp, a0
|
|
; RV32I-NEXT: lw s0, 2024(sp)
|
|
; RV32I-NEXT: lw ra, 2028(sp)
|
|
; RV32I-NEXT: addi sp, sp, 2032
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: caller4096:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -2032
|
|
; RV64I-NEXT: sd ra, 2024(sp)
|
|
; RV64I-NEXT: sd s0, 2016(sp)
|
|
; RV64I-NEXT: addi s0, sp, 2032
|
|
; RV64I-NEXT: lui a0, 3
|
|
; RV64I-NEXT: addiw a0, a0, -2032
|
|
; RV64I-NEXT: sub sp, sp, a0
|
|
; RV64I-NEXT: srli a0, sp, 12
|
|
; RV64I-NEXT: slli sp, a0, 12
|
|
; RV64I-NEXT: lui a0, 2
|
|
; RV64I-NEXT: add a0, sp, a0
|
|
; RV64I-NEXT: mv a0, a0
|
|
; RV64I-NEXT: call callee
|
|
; RV64I-NEXT: lui a0, 3
|
|
; RV64I-NEXT: sub sp, s0, a0
|
|
; RV64I-NEXT: lui a0, 3
|
|
; RV64I-NEXT: addiw a0, a0, -2032
|
|
; RV64I-NEXT: add sp, sp, a0
|
|
; RV64I-NEXT: ld s0, 2016(sp)
|
|
; RV64I-NEXT: ld ra, 2024(sp)
|
|
; RV64I-NEXT: addi sp, sp, 2032
|
|
; RV64I-NEXT: ret
|
|
%1 = alloca i8, align 4096
|
|
call void @callee(i8* %1)
|
|
ret void
|
|
}
|
|
|
|
define void @caller_no_realign4096() nounwind "no-realign-stack" {
|
|
; RV32I-LABEL: caller_no_realign4096:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: mv a0, sp
|
|
; RV32I-NEXT: call callee
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: caller_no_realign4096:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: mv a0, sp
|
|
; RV64I-NEXT: call callee
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
%1 = alloca i8, align 4096
|
|
call void @callee(i8* %1)
|
|
ret void
|
|
}
|