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https://github.com/RPCS3/llvm-mirror.git
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535690cd25
Change to expand MULHU/MULHS/UMUL_LOHI/SMUL_LOHI for i32 and i64 since those instructions are not available on Aurora SX VE. Some of them are used in expansion of i128 multiply, so need to modify them to support i128. Then, update basic arithmetic regression tests of i128 and signed/unsigned i32 typed integer values. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D85490
270 lines
7.4 KiB
LLVM
270 lines
7.4 KiB
LLVM
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
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; Function Attrs: norecurse nounwind readnone
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define i128 @divi128(i128, i128) {
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; CHECK-LABEL: divi128:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: lea %s4, __divti3@lo
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; CHECK-NEXT: and %s4, %s4, (32)0
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; CHECK-NEXT: lea.sl %s12, __divti3@hi(, %s4)
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; CHECK-NEXT: bsic %s10, (, %s12)
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = sdiv i128 %0, %1
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ret i128 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @divi64(i64 %a, i64 %b) {
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; CHECK-LABEL: divi64:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divs.l %s0, %s0, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = sdiv i64 %a, %b
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ret i64 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @divi32(i32 signext %a, i32 signext %b) {
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; CHECK-LABEL: divi32:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divs.w.sx %s0, %s0, %s1
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = sdiv i32 %a, %b
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ret i32 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define i128 @divu128(i128, i128) {
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; CHECK-LABEL: divu128:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: lea %s4, __udivti3@lo
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; CHECK-NEXT: and %s4, %s4, (32)0
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; CHECK-NEXT: lea.sl %s12, __udivti3@hi(, %s4)
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; CHECK-NEXT: bsic %s10, (, %s12)
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = udiv i128 %0, %1
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ret i128 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @divu64(i64 %a, i64 %b) {
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; CHECK-LABEL: divu64:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divu.l %s0, %s0, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = udiv i64 %a, %b
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ret i64 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i32 @divu32(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-LABEL: divu32:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divu.w %s0, %s0, %s1
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; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = udiv i32 %a, %b
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ret i32 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i16 @divi16(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: divi16:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divs.w.sx %s0, %s0, %s1
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; CHECK-NEXT: sll %s0, %s0, 48
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; CHECK-NEXT: sra.l %s0, %s0, 48
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; CHECK-NEXT: or %s11, 0, %s9
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%a32 = sext i16 %a to i32
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%b32 = sext i16 %b to i32
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%r32 = sdiv i32 %a32, %b32
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%r = trunc i32 %r32 to i16
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ret i16 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i16 @divu16(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: divu16:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divu.w %s0, %s0, %s1
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; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = udiv i16 %a, %b
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ret i16 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i8 @divi8(i8 signext %a, i8 signext %b) {
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; CHECK-LABEL: divi8:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divs.w.sx %s0, %s0, %s1
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; CHECK-NEXT: sll %s0, %s0, 56
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; CHECK-NEXT: sra.l %s0, %s0, 56
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; CHECK-NEXT: or %s11, 0, %s9
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%a32 = sext i8 %a to i32
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%b32 = sext i8 %b to i32
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%r32 = sdiv i32 %a32, %b32
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%r = trunc i32 %r32 to i8
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ret i8 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i8 @divu8(i8 zeroext %a, i8 zeroext %b) {
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; CHECK-LABEL: divu8:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divu.w %s0, %s0, %s1
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; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = udiv i8 %a, %b
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ret i8 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define i128 @divi128ri(i128) {
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; CHECK-LABEL: divi128ri:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: lea %s2, __divti3@lo
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; CHECK-NEXT: and %s2, %s2, (32)0
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; CHECK-NEXT: lea.sl %s12, __divti3@hi(, %s2)
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; CHECK-NEXT: or %s2, 3, (0)1
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; CHECK-NEXT: or %s3, 0, (0)1
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; CHECK-NEXT: bsic %s10, (, %s12)
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; CHECK-NEXT: or %s11, 0, %s9
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%2 = sdiv i128 %0, 3
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ret i128 %2
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @divi64ri(i64 %a, i64 %b) {
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; CHECK-LABEL: divi64ri:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divs.l %s0, %s0, (62)0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = sdiv i64 %a, 3
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ret i64 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @divi32ri(i32 signext %a, i32 signext %b) {
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; CHECK-LABEL: divi32ri:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divs.w.sx %s0, %s0, (62)0
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = sdiv i32 %a, 3
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ret i32 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define i128 @divu128ri(i128) {
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; CHECK-LABEL: divu128ri:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: lea %s2, __udivti3@lo
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; CHECK-NEXT: and %s2, %s2, (32)0
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; CHECK-NEXT: lea.sl %s12, __udivti3@hi(, %s2)
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; CHECK-NEXT: or %s2, 3, (0)1
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; CHECK-NEXT: or %s3, 0, (0)1
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; CHECK-NEXT: bsic %s10, (, %s12)
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; CHECK-NEXT: or %s11, 0, %s9
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%2 = udiv i128 %0, 3
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ret i128 %2
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @divu64ri(i64 %a, i64 %b) {
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; CHECK-LABEL: divu64ri:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divu.l %s0, %s0, (62)0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = udiv i64 %a, 3
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ret i64 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i32 @divu32ri(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-LABEL: divu32ri:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divu.w %s0, %s0, (62)0
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; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = udiv i32 %a, 3
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ret i32 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define i128 @divi128li(i128) {
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; CHECK-LABEL: divi128li:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s3, 0, %s1
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; CHECK-NEXT: or %s2, 0, %s0
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; CHECK-NEXT: lea %s0, __divti3@lo
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea.sl %s12, __divti3@hi(, %s0)
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; CHECK-NEXT: or %s0, 3, (0)1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: bsic %s10, (, %s12)
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; CHECK-NEXT: or %s11, 0, %s9
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%2 = sdiv i128 3, %0
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ret i128 %2
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @divi64li(i64 %a, i64 %b) {
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; CHECK-LABEL: divi64li:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divs.l %s0, 3, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = sdiv i64 3, %b
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ret i64 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @divi32li(i32 signext %a, i32 signext %b) {
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; CHECK-LABEL: divi32li:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divs.w.sx %s0, 3, %s1
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = sdiv i32 3, %b
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ret i32 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define i128 @divu128li(i128) {
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; CHECK-LABEL: divu128li:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s3, 0, %s1
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; CHECK-NEXT: or %s2, 0, %s0
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; CHECK-NEXT: lea %s0, __udivti3@lo
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea.sl %s12, __udivti3@hi(, %s0)
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; CHECK-NEXT: or %s0, 3, (0)1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: bsic %s10, (, %s12)
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; CHECK-NEXT: or %s11, 0, %s9
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%2 = udiv i128 3, %0
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ret i128 %2
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @divu64li(i64 %a, i64 %b) {
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; CHECK-LABEL: divu64li:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divu.l %s0, 3, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = udiv i64 3, %b
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ret i64 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i32 @divu32li(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-LABEL: divu32li:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divu.w %s0, 3, %s1
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; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = udiv i32 3, %b
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ret i32 %r
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}
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