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6183095839
Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
48 lines
1.8 KiB
LLVM
48 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -fast-isel -mtriple=i686-unknown -mattr=+avx512cd | FileCheck %s --check-prefixes=CHECK,X86
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; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown -mattr=+avx512cd | FileCheck %s --check-prefixes=CHECK,X64
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define <8 x i64> @test_mm512_broadcastmb_epi64(<8 x i64> %a, <8 x i64> %b) {
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; X86-LABEL: test_mm512_broadcastmb_epi64:
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; X86: # %bb.0: # %entry
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; X86-NEXT: vpcmpeqq %zmm1, %zmm0, %k0
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; X86-NEXT: kmovw %k0, %eax
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; X86-NEXT: movzbl %al, %eax
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; X86-NEXT: vmovd %eax, %xmm0
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; X86-NEXT: vpbroadcastq %xmm0, %zmm0
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; X86-NEXT: retl
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;
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; X64-LABEL: test_mm512_broadcastmb_epi64:
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; X64: # %bb.0: # %entry
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; X64-NEXT: vpcmpeqq %zmm1, %zmm0, %k0
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; X64-NEXT: vpbroadcastmb2q %k0, %zmm0
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; X64-NEXT: retq
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entry:
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%0 = icmp eq <8 x i64> %a, %b
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%1 = bitcast <8 x i1> %0 to i8
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%conv.i = zext i8 %1 to i64
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%vecinit.i.i = insertelement <8 x i64> undef, i64 %conv.i, i32 0
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%vecinit7.i.i = shufflevector <8 x i64> %vecinit.i.i, <8 x i64> undef, <8 x i32> zeroinitializer
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ret <8 x i64> %vecinit7.i.i
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}
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define <8 x i64> @test_mm512_broadcastmw_epi32(<8 x i64> %a, <8 x i64> %b) {
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; CHECK-LABEL: test_mm512_broadcastmw_epi32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
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; CHECK-NEXT: vpbroadcastmw2d %k0, %zmm0
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; CHECK-NEXT: ret{{[l|q]}}
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entry:
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%0 = bitcast <8 x i64> %a to <16 x i32>
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%1 = bitcast <8 x i64> %b to <16 x i32>
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%2 = icmp eq <16 x i32> %0, %1
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%3 = bitcast <16 x i1> %2 to i16
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%conv.i = zext i16 %3 to i32
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%vecinit.i.i = insertelement <16 x i32> undef, i32 %conv.i, i32 0
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%vecinit15.i.i = shufflevector <16 x i32> %vecinit.i.i, <16 x i32> undef, <16 x i32> zeroinitializer
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%4 = bitcast <16 x i32> %vecinit15.i.i to <8 x i64>
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ret <8 x i64> %4
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}
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