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ae37969223
-fuse-init-array is now the CC1 default but TargetLoweringObjectFileELF::UseInitArray still defaults to false. The following two unknown OS target triples continue using .ctors/.dtors because InitializeELF is not called. clang -target i386 -c a.c clang -target x86_64 -c a.c This cleanup fixes this as a bonus. X86SpeculativeLoadHardeningPass::tracePredStateThroughCall can call MCContext::createTempSymbol before TargetLoweringObjectFileELF::Initialize(). We need to call TargetLoweringObjectFileELF::Initialize() ealier. test/CodeGen/X86/speculative-load-hardening-indirect.ll Differential Revision: https://reviews.llvm.org/D71360
73 lines
2.7 KiB
LLVM
73 lines
2.7 KiB
LLVM
; RUN: llc -mtriple x86_64 < %s | FileCheck --check-prefix=INIT-ARRAY %s
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; RUN: llc -mtriple x86_64-pc-linux -use-ctors < %s | FileCheck --check-prefix=CTOR %s
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; RUN: llc -mtriple x86_64-unknown-freebsd -use-ctors < %s | FileCheck --check-prefix=CTOR %s
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; RUN: llc -mtriple x86_64-pc-solaris2.11 -use-ctors < %s | FileCheck --check-prefix=CTOR %s
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; RUN: llc -mtriple x86_64-pc-linux < %s | FileCheck --check-prefix=INIT-ARRAY %s
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; RUN: llc -mtriple x86_64-unknown-freebsd < %s | FileCheck --check-prefix=INIT-ARRAY %s
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; RUN: llc -mtriple x86_64-pc-solaris2.11 < %s | FileCheck --check-prefix=INIT-ARRAY %s
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; RUN: llc -mtriple x86_64-unknown-nacl < %s | FileCheck --check-prefix=NACL %s
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; RUN: llc -mtriple i586-intel-elfiamcu -use-ctors < %s | FileCheck %s --check-prefix=MCU-CTORS
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; RUN: llc -mtriple i586-intel-elfiamcu < %s | FileCheck %s --check-prefix=MCU-INIT-ARRAY
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; RUN: llc -mtriple x86_64-win32-gnu < %s | FileCheck --check-prefix=COFF-CTOR %s
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@llvm.global_ctors = appending global [3 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @f, i8* null}, { i32, void ()*, i8* } { i32 15, void ()* @g, i8* @v }, { i32, void ()*, i8* } { i32 55555, void ()* @h, i8* @v }]
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@v = weak_odr global i8 0
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define void @f() {
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entry:
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ret void
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}
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define void @g() {
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entry:
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ret void
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}
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define void @h() {
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entry:
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ret void
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}
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; CTOR: .section .ctors.65520,"aGw",@progbits,v,comdat
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; CTOR-NEXT: .p2align 3
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; CTOR-NEXT: .quad g
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; CTOR-NEXT: .section .ctors.09980,"aGw",@progbits,v,comdat
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; CTOR-NEXT: .p2align 3
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; CTOR-NEXT: .quad h
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; CTOR-NEXT: .section .ctors,"aw",@progbits
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; CTOR-NEXT: .p2align 3
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; CTOR-NEXT: .quad f
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; INIT-ARRAY: .section .init_array.15,"aGw",@init_array,v,comdat
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; INIT-ARRAY-NEXT: .p2align 3
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; INIT-ARRAY-NEXT: .quad g
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; INIT-ARRAY-NEXT: .section .init_array.55555,"aGw",@init_array,v,comdat
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; INIT-ARRAY-NEXT: .p2align 3
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; INIT-ARRAY-NEXT: .quad h
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; INIT-ARRAY-NEXT: .section .init_array,"aw",@init_array
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; INIT-ARRAY-NEXT: .p2align 3
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; INIT-ARRAY-NEXT: .quad f
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; NACL: .section .init_array.15,"aGw",@init_array,v,comdat
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; NACL-NEXT: .p2align 2
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; NACL-NEXT: .long g
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; NACL-NEXT: .section .init_array.55555,"aGw",@init_array,v,comdat
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; NACL-NEXT: .p2align 2
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; NACL-NEXT: .long h
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; NACL-NEXT: .section .init_array,"aw",@init_array
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; NACL-NEXT: .p2align 2
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; NACL-NEXT: .long f
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; MCU-CTORS: .section .ctors,"aw",@progbits
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; MCU-INIT-ARRAY: .section .init_array,"aw",@init_array
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; COFF-CTOR: .section .ctors.65520,"dw",associative,v
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; COFF-CTOR-NEXT: .p2align 3
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; COFF-CTOR-NEXT: .quad g
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; COFF-CTOR-NEXT: .section .ctors.09980,"dw",associative,v
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; COFF-CTOR-NEXT: .p2align 3
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; COFF-CTOR-NEXT: .quad h
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; COFF-CTOR-NEXT: .section .ctors,"dw"
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; COFF-CTOR-NEXT: .p2align 3
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; COFF-CTOR-NEXT: .quad f
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