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a4615b0a89
Previously we just updated a map and moved on. But it possible we cached known bits information with the vreg that can be used by another basic block. If the other basic block has a different view of the VT these known bits won't make sense. By emitting a copy we ensure we have different vregs before and after the bitcast. This prevents the known bits from being used with the wrong type. Differential Revision: https://reviews.llvm.org/D82517
45 lines
1.7 KiB
LLVM
45 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -fast-isel -O1 | FileCheck %s
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; This used to crash due to the bitcast in the entry block reusing the vreg
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; from its input. This resulted in known bits being calculated on the v2i64
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; type. But the second basic block tried to use them with a v8i16 type. This
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; was fixed by emitting a reg-reg copy for the bitcast so the vreg type will
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; be seen the same in both basic blocks.
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; We need the entry block to fall out of fast isel after selecting the bitcast.
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; The shuffle vector guarantees that. The zext gives us a useful known bits
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; value. We also need the second basic block to fall out of fast isel which the
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; intrinsic guarantees.
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define <8 x i16> @bitcast_crash(i32 %arg, <8 x i16> %x, i1 %c) {
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; CHECK-LABEL: bitcast_crash:
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; CHECK: # %bb.0: # %bb
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: movq %rax, %xmm1
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; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
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; CHECK-NEXT: testb $1, %sil
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; CHECK-NEXT: je .LBB0_2
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; CHECK-NEXT: # %bb.1: # %bb1
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; CHECK-NEXT: psraw %xmm1, %xmm0
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB0_2: # %bb2
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; CHECK-NEXT: movdqa %xmm1, %xmm0
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; CHECK-NEXT: retq
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bb:
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%tmp = zext i32 %arg to i64
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%tmp1 = insertelement <2 x i64> undef, i64 %tmp, i32 0
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%tmp2 = shufflevector <2 x i64> %tmp1, <2 x i64> undef, <2 x i32> zeroinitializer
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%tmp5 = bitcast <2 x i64> %tmp2 to <8 x i16>
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br i1 %c, label %bb1, label %bb2
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bb1: ; preds = %bb8, %bb6
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%tmp9 = call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %x, <8 x i16> %tmp5)
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ret <8 x i16> %tmp9
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bb2:
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ret <8 x i16> %tmp5
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}
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declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>)
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