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d654e7d40c
Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
198 lines
6.5 KiB
LLVM
198 lines
6.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSEANY --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSEANY --check-prefix=SSE4
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX
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define <4 x i32> @ins_elt_0(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
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; SSE2-LABEL: ins_elt_0:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: movd %edi, %xmm1
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; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSE2-NEXT: retq
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;
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; SSE4-LABEL: ins_elt_0:
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; SSE4: # %bb.0:
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; SSE4-NEXT: movdqa %xmm1, %xmm0
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; SSE4-NEXT: pinsrd $0, %edi, %xmm0
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; SSE4-NEXT: retq
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;
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; AVX-LABEL: ins_elt_0:
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; AVX: # %bb.0:
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; AVX-NEXT: vpinsrd $0, %edi, %xmm1, %xmm0
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; AVX-NEXT: retq
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%ins = insertelement <4 x i32> %v1, i32 %x, i32 0
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%shuf = shufflevector <4 x i32> %ins, <4 x i32> %v2, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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ret <4 x i32> %shuf
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}
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define <4 x i32> @ins_elt_1(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
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; SSE2-LABEL: ins_elt_1:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movd %edi, %xmm0
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
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; SSE2-NEXT: retq
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;
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; SSE4-LABEL: ins_elt_1:
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; SSE4: # %bb.0:
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; SSE4-NEXT: movdqa %xmm1, %xmm0
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; SSE4-NEXT: pinsrd $1, %edi, %xmm0
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; SSE4-NEXT: retq
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;
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; AVX-LABEL: ins_elt_1:
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; AVX: # %bb.0:
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; AVX-NEXT: vpinsrd $1, %edi, %xmm1, %xmm0
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; AVX-NEXT: retq
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%ins = insertelement <4 x i32> %v1, i32 %x, i32 1
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%shuf = shufflevector <4 x i32> %ins, <4 x i32> %v2, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
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ret <4 x i32> %shuf
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}
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; Verify that the transform still works when the insert element is the 2nd operand to the shuffle.
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define <4 x i32> @ins_elt_2_commute(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
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; SSE2-LABEL: ins_elt_2_commute:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: movd %edi, %xmm1
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
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; SSE2-NEXT: retq
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;
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; SSE4-LABEL: ins_elt_2_commute:
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; SSE4: # %bb.0:
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; SSE4-NEXT: movdqa %xmm1, %xmm0
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; SSE4-NEXT: pinsrd $2, %edi, %xmm0
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; SSE4-NEXT: retq
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;
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; AVX-LABEL: ins_elt_2_commute:
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; AVX: # %bb.0:
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; AVX-NEXT: vpinsrd $2, %edi, %xmm1, %xmm0
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; AVX-NEXT: retq
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%ins = insertelement <4 x i32> %v1, i32 %x, i32 2
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%shuf = shufflevector <4 x i32> %v2, <4 x i32> %ins, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
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ret <4 x i32> %shuf
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}
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define <4 x i32> @ins_elt_3_commute(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
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; SSE2-LABEL: ins_elt_3_commute:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: movd %edi, %xmm1
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
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; SSE2-NEXT: retq
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;
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; SSE4-LABEL: ins_elt_3_commute:
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; SSE4: # %bb.0:
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; SSE4-NEXT: movdqa %xmm1, %xmm0
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; SSE4-NEXT: pinsrd $3, %edi, %xmm0
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; SSE4-NEXT: retq
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;
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; AVX-LABEL: ins_elt_3_commute:
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; AVX: # %bb.0:
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; AVX-NEXT: vpinsrd $3, %edi, %xmm1, %xmm0
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; AVX-NEXT: retq
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%ins = insertelement <4 x i32> %v1, i32 %x, i32 3
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%shuf = shufflevector <4 x i32> %v2, <4 x i32> %ins, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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ret <4 x i32> %shuf
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}
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; In the next 4 tests, the shuffle moves the inserted scalar to a different position in the output vector.
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define <4 x i32> @ins_elt_0_to_2(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
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; SSE2-LABEL: ins_elt_0_to_2:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: movd %edi, %xmm1
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
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; SSE2-NEXT: retq
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;
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; SSE4-LABEL: ins_elt_0_to_2:
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; SSE4: # %bb.0:
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; SSE4-NEXT: movdqa %xmm1, %xmm0
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; SSE4-NEXT: pinsrd $2, %edi, %xmm0
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; SSE4-NEXT: retq
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;
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; AVX-LABEL: ins_elt_0_to_2:
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; AVX: # %bb.0:
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; AVX-NEXT: vpinsrd $2, %edi, %xmm1, %xmm0
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; AVX-NEXT: retq
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%ins = insertelement <4 x i32> %v1, i32 %x, i32 0
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%shuf = shufflevector <4 x i32> %ins, <4 x i32> %v2, <4 x i32> <i32 4, i32 5, i32 0, i32 7>
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ret <4 x i32> %shuf
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}
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define <4 x i32> @ins_elt_1_to_0(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
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; SSE2-LABEL: ins_elt_1_to_0:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: movd %edi, %xmm1
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; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSE2-NEXT: retq
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;
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; SSE4-LABEL: ins_elt_1_to_0:
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; SSE4: # %bb.0:
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; SSE4-NEXT: movdqa %xmm1, %xmm0
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; SSE4-NEXT: pinsrd $0, %edi, %xmm0
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; SSE4-NEXT: retq
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;
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; AVX-LABEL: ins_elt_1_to_0:
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; AVX: # %bb.0:
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; AVX-NEXT: vpinsrd $0, %edi, %xmm1, %xmm0
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; AVX-NEXT: retq
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%ins = insertelement <4 x i32> %v1, i32 %x, i32 1
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%shuf = shufflevector <4 x i32> %ins, <4 x i32> %v2, <4 x i32> <i32 1, i32 5, i32 6, i32 7>
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ret <4 x i32> %shuf
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}
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define <4 x i32> @ins_elt_2_to_3(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
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; SSE2-LABEL: ins_elt_2_to_3:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: movd %edi, %xmm1
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
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; SSE2-NEXT: retq
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;
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; SSE4-LABEL: ins_elt_2_to_3:
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; SSE4: # %bb.0:
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; SSE4-NEXT: movdqa %xmm1, %xmm0
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; SSE4-NEXT: pinsrd $3, %edi, %xmm0
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; SSE4-NEXT: retq
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;
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; AVX-LABEL: ins_elt_2_to_3:
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; AVX: # %bb.0:
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; AVX-NEXT: vpinsrd $3, %edi, %xmm1, %xmm0
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; AVX-NEXT: retq
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%ins = insertelement <4 x i32> %v1, i32 %x, i32 2
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%shuf = shufflevector <4 x i32> %v2, <4 x i32> %ins, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
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ret <4 x i32> %shuf
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}
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define <4 x i32> @ins_elt_3_to_1(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
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; SSE2-LABEL: ins_elt_3_to_1:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movd %edi, %xmm0
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
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; SSE2-NEXT: retq
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;
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; SSE4-LABEL: ins_elt_3_to_1:
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; SSE4: # %bb.0:
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; SSE4-NEXT: movdqa %xmm1, %xmm0
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; SSE4-NEXT: pinsrd $1, %edi, %xmm0
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; SSE4-NEXT: retq
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;
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; AVX-LABEL: ins_elt_3_to_1:
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; AVX: # %bb.0:
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; AVX-NEXT: vpinsrd $1, %edi, %xmm1, %xmm0
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; AVX-NEXT: retq
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%ins = insertelement <4 x i32> %v1, i32 %x, i32 3
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%shuf = shufflevector <4 x i32> %v2, <4 x i32> %ins, <4 x i32> <i32 0, i32 7, i32 2, i32 3>
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ret <4 x i32> %shuf
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}
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