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908ef3f208
Currently custom code predicates can only really be used for contextless checks tied to a single instruction (e.g. check the def for hasOneUse). If you do want to inspect the input instructions in the source pattern, you cannot without re-verifying the opcode and type checks implied by the patterns, since this check was emitted before any operand constraints. Really, these are pattern level predicates that implicitly depend on the instruction and operand checks. Introduce a filtering function so the custom predicate is emitted last. I'm not sure this is the most elegant solution. It seems like this is really a different thing from the InstructionMatcher/IPM_ predicate kinds. I initially tried keeping this in a separate predicate list, but that also seemed awkward. This only half fixes the problem I'm trying to solve. The AMDGPU pattern I'm attempting to port also uses the PredicateCodeUsesOperands feature to allow checks on the source operands when the input pattern is commuted. Really the emitter should reject the pattern since it doesn't handle this case, but at this point it would be more productive to just implement this.
149 lines
6.8 KiB
TableGen
149 lines
6.8 KiB
TableGen
// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
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include "llvm/Target/Target.td"
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include "GlobalISelEmitterCommon.td"
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// Boilerplate code for setting up some registers with subregs.
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class MyReg<string n, list<Register> subregs = []>
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: Register<n> {
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let SubRegs = subregs;
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}
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class MyClass<int size, list<ValueType> types, dag registers>
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: RegisterClass<"Test", types, size, registers> {
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let Size = size;
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}
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def sub0 : SubRegIndex<16>;
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def sub1 : SubRegIndex<16, 16>;
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def S0 : MyReg<"s0">;
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def S1 : MyReg<"s1">;
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def SRegs : MyClass<16, [i16], (sequence "S%u", 0, 1)>;
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let SubRegIndices = [sub0, sub1] in {
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def D0 : MyReg<"d0", [S0, S1]>;
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}
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def DRegs : MyClass<32, [i32], (sequence "D%u", 0, 0)>;
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def DOP : RegisterOperand<DRegs>;
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def AND_OR : I<(outs DRegs:$dst), (ins DOP:$src0, DOP:$src1, DOP:$src2), []>;
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def or_oneuse : PatFrag<
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(ops node:$x, node:$y),
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(or node:$x, node:$y), [{ return foo(); }]> {
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let GISelPredicateCode = [{
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return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
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}];
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}
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// FIXME: GISelPredicateCode ignored if DAG predicate not set.
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def and_or_pat : PatFrag<
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(ops node:$x, node:$y, node:$z),
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(and (or node:$x, node:$y), node:$z), [{ return foo(); }]> {
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let GISelPredicateCode = [{
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return doesComplexCheck(MI);
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}];
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}
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// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ {{[0-9]+}}, // Rule ID 1 //
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// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
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// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_AND,
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// CHECK-NEXT: // MIs[0] dst
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// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Test::DRegsRegClassID,
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// CHECK-NEXT: // MIs[0] Operand 1
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// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
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// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
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// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
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// CHECK-NEXT: // MIs[1] Operand 0
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// CHECK-NEXT:GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
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// CHECK-NEXT: // MIs[1] src0
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// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Test::DRegsRegClassID,
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// CHECK-NEXT: // MIs[1] src1
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// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Test::DRegsRegClassID,
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// CHECK-NEXT: // MIs[0] src2
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// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Test::DRegsRegClassID,
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// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_and_or_pat,
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// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
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// CHECK-NEXT: // (and:{ *:[i32] } (or:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1), DOP:{ *:[i32] }:$src2)<<P:Predicate_and_or_pat>> => (AND_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2)
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::AND_OR,
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// CHECK: GIM_Try, /*On fail goto*//*Label 1*/ {{[0-9]+}}, // Rule ID 2 //
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// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
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// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_AND,
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// CHECK-NEXT: // MIs[0] dst
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// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Test::DRegsRegClassID,
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// CHECK-NEXT: // MIs[0] src2
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// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Test::DRegsRegClassID,
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// CHECK-NEXT: // MIs[0] Operand 2
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// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
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// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
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// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
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// CHECK-NEXT: // MIs[1] Operand 0
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// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
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// CHECK-NEXT: // MIs[1] src0
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// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Test::DRegsRegClassID,
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// CHECK-NEXT: // MIs[1] src1
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// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Test::DRegsRegClassID,
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// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_and_or_pat,
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// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
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// CHECK-NEXT: // (and:{ *:[i32] } DOP:{ *:[i32] }:$src2, (or:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1))<<P:Predicate_and_or_pat>> => (AND_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2)
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::AND_OR,
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// Test commutative, standalone pattern.
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def : Pat<
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(i32 (and_or_pat DOP:$src0, DOP:$src1, DOP:$src2)),
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(AND_OR DOP:$src0, DOP:$src1, DOP:$src2)
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>;
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def sub3_pat : PatFrag<
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(ops node:$x, node:$y, node:$z),
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(sub (sub node:$x, node:$y), node:$z), [{ return foo(); }]> {
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let GISelPredicateCode = [{
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return doesComplexCheck(MI);
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}];
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}
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// CHECK: GIM_Try, /*On fail goto*//*Label 2*/ {{[0-9]+}}, // Rule ID 0 //
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// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
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// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB,
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// CHECK-NEXT: // MIs[0] dst
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// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Test::DRegsRegClassID,
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// CHECK-NEXT: // MIs[0] Operand 1
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// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
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// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
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// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
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// CHECK-NEXT: // MIs[1] Operand 0
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// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
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// CHECK-NEXT: // MIs[1] src0
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// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
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// CHECK-NEXT: // MIs[1] src1
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// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
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// CHECK-NEXT: // MIs[0] src2
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// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_sub3_pat,
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// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
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// CHECK-NEXT: // (sub:{ *:[i32] } (sub:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2)<<P:Predicate_sub3_pat>> => (SUB3:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SUB3,
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// Test a non-commutative pattern.
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def SUB3 : I<(outs DRegs:$dst),
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(ins DOP:$src0, DOP:$src1, DOP:$src2),
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[(set DRegs:$dst, (sub3_pat i32:$src0, i32:$src1, i32:$src2))]
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>;
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